[Coco] CoCo 1 64K upgrade failed :(.

[Ryan Pritchard]

I don't understand why the SAM is only refreshing at 128 cycles.  You have 8
address bits getting latched on RAS and then the next 8 bit being latched on
CAS.   Wouldn't 8 address bits mean 256 cycles?  Or is the refresh occuring
for 2 rows per cycle?

On Fri, Sep 26, 2008 at 3:55 PM, Chuck Youse
<cyouse at serialtechnologies.com>wrote:

> On Fri, 2008-09-26 at 21:46 +0100, Phill Harvey-Smith wrote:
>
> > My answer to that would have to be 'maybe' I have done this on a Dragon
> > 32 board and it did seem to work ok, however it is out of spec as the
> > 74LS783 SAM can only do 128 cycle refresh, where as the 41256 type chips
> > need 256 cycle refresh however like I said I tried it and it did seem to
> > work, so may be worth a shot.
>
> Ah, but if you're only using the lower half, only the lower half needs a
> refresh, no? :)
>
> Talking out of my ass here, don't remember the innards of DRAMs anymore,
> but I don't see the need to recharge the caps in the unused
> rows/columns.
>
> C.
>
>
>
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-- 
Regards,

Ryan Pritchard
Fun Extends All Basic Life Expectancies