[Coco] MCM68766

[Chuck Youse]

On Mon, 2008-07-14 at 10:59 -0400, jdaggett at gate.net wrote:

> 
> Access time of ROMS is equal to the read cycle time. Thus for an access time of 350nS that 
> is speced from the time that the address is valid to the time that the data is outputed from 
> the ROM. In the 6809 the address is valid approxiamtely on the falling edge of the Q Clock. 
> Data is clocked into the processor on  the next falling edge of the E Clock. The 6809 cycle 
> starts on the falling edge of the Eclock.

Actually, the address is valid on the *positive* edge of the Q clock,
and remains valid until the negative edge of the E clock.  But most
6800-family MPUs don't have the quadrature clock, and as such the 6800
peripherals only have E inputs.  On the positive edge of E, bus signals
are assumed valid, and a bus cycle is in progress; it ends on the
negative edge.  

Thus, at 2MHz your access time is 1/2 of E, which is 250ns (roughly).

As for the ROMs in question, you make a good point that ROMs are
read-only devices, and therefore I think there's a good chance that
350ns versions would work on the Coco at 1.78MHz -- from the datasheet:

1. the address-valid to output-valid time (access time) is 350ns;
2. output-enable to output-valid time is 150ns.

At 1.78MHz, address-valid to CPU-latch of data (Q rise to E fall) is
~420ns.

The only question is what the timings look like for address-valid before
output-enable, which the datasheet I have doesn't address.  It all
depends on the timing of S[2:0] from the GIME, as they're responsible
for OE* on the ROM.

In any case, I still don't see what this has to do with interleaved DMA
for video. :)

C.