[Coco] "Reading" non-readable bytes with PEEK vs ZBUG

[jdaggett at gate.net]

On 22 Jan 2008 at 17:21, Darren A. wrote:

> James,
> 
> Do you have a copy of the 6809 datasheet handy? If you look at the
> cycle flowchart for the Indexed Addressing Mode, it shows that during
> cycle 3, the address bus is NNNN+2 (where NNNN is the opcode address)
> and the data bus is "Dont Care". In the case of LDB ,X this cycle
> immediately precedes the one where the data is loaded from the
> effective address. Doesn't this mean that a read of NNNN+2 occurs one
> cycle before a read of the effective address? It sure seems to fit
> with the results we are seeing.
> 
> Darren

Darren

In answer to your question, no. Look back up and see where the post byte is loaded in cycle 
#2. It also reads NNNN+2. By that chart the address buss at cycle 3 is still pointing to the 
address after the postbyte. At some point in the four cycles the address will have to be what 
is in the contents of the X register and not the PCR(NNNN+2).

When the actual data is read the value of the X register is latched to the address buss and 
not the contents of the PCR. During cycle four the PCR is incremented and then latched to 
the address buss. Ready for the next opcode fetch. 

I would not put to much faith in those charts. They grant a decent idea as to what the CPU 
is doing but when you start to get into the nuts and bolts you will find that it is lacking in 
many ways.
 
You maybe very well correct inthat the next opcode is causing the problems. I stil think you 
are looking at the wrong IC. I still believe it is the GIME chip and not the 6809. You are now 
chasing red herrings. 

james