[Coco] CoCo 3 display offset question.

[Robert Gault]

Phill Harvey-Smith wrote:
> Hi,
> 
> Can anyone tell me if on the CoCo 3 the display generation in the GIME 
> goes through the mapped memory or if it is limited to a particular block 
> (or blocks). A quick check using mess seems to suggest that it honours 
> the tradition display offset regs at $FFC6-$FFD3, but I just verified 
> this with a quick 4 line basic program, which will have had the mapping 
> regs turned off (well CoCo 1/2 compatible mode anyway).
> 
> I'm asking as one of the things I am working on is to use a 1M 30 pin 
> SIMM, and build a banked system for the CoCo 1/2 & Dragon, using a CPLD, 
>  a small SRAM to do the banking. The current design however takes the 
> Address bus input to the SAM, and modifies this through the bank 
> registers before it goes into the SAM. This should work as far as the 
> CPU is concerned, but a side effect may well be that the CPU and the VDG 
> will see the display memory differently, whilst this probably won't be a 
> problem it's something I'll have to bear in mind :)
> 
> Cheers,
> 
> Phill.
> 

There are several aspects to your questions that need clarification. The 
problematic wording is "goes through the mapped memory".

There are two different operations on the Coco, 1) manipulating bytes in 
memory, 2) displaying bytes in memory as video information. These two 
operations are completely independent from each other. For data to be 
read/written the memory must be within the CPU 64k address space. The 
video circuitry can display any memory whether it is within the CPU 64K 
address space or not.

Since the SAM addressing used on the Coco1&2 is simulated on the Coco3 
by the GIME chip, all addressing goes through the GIME even if it seems 
to use the SAM address locations.

Now as to where memory must be mapped for access, it can be anywhere 
that does not interfere with system or program code. It is not necessary 
to map memory just to display it. However, the design of the Coco is 
such that the video memory must be linear so that when mapped into the 
64K CPU address space the video memory lines up with the actual memory. 
Put another way, if you want to display
    xxx          xxx
       xxx    xxx
          xxxx
on the screen you alter the mapped memory in exactly that bit pattern 
when the resolution is 1 bit per pixel.