[Coco] PICs and S-Video

John Kowalski sock at axess.com
Thu Feb 23 22:24:25 EST 2006

At 08:25 PM 23/02/2006 -0600, Chris Hawks wrote:
>> HSYNC in    ________--____________________--____________________--______
>> timer 1     __________---------------_______---------------_______------
>> timer 2     _________________________--____________________--___________
>> (HSYNC out)
>> -Timer 1 would trigger when the HSYNC goes low and Timer 1's output would
>> remain high for the duration of the delay period.
>> -Timer 2 would trigger when the output of Timer 1 goes low and the output
>> would be the new delayed HSYNC signal.
>    Thats' what I thought 'til I found out that the output will ALLWAYS be
>high when the input is low. So the output of timer 1 is not what you show,
>timer 1

You could try putting some very small capacitors in series with the trigger
inputs to filter out the DC component of the signal, and only let short
spikes through at the transitions between high and low.  (And a resistor
pull up the level so that only the lowest peak crosses into "low" and the
rest registers as "high" to the chip.)

I'm thinking of adding HSYNC delay to my RGB-to-Svideo converter as well, so
I'm going to try using a 556 on mine as well.

                                         John Kowalski (Sock Master)

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