[Coco] Timing problem with the CoCo and the WD1773 ?

[Gene Heskett]

On Monday 07 August 2006 23:29, Robert Gault wrote:
>The important part of this doc is not even/odd bytes. That just uncovers
>timing problems in the 1773. The critical answer to the problem is
>not to reload $FF40 in the read/write loops.
>
>That means you don't use a loop such as
>readloop lda       $ff4b     get a data byte
>          sta       ,x+       store it in the buffer, point to next cell
>          stb       $ff40     enable halt mode
>          bra       readloop  continue till NMI
>
>Instead you use
>readloop  lda       $ff4b     get data from fdc
>           sta       ,x+       store byte in buffer
>           nop                 one more op code fetch for HALT
>           bra       readloop  repeat till NMI occurs

But now its married rather intimately to the cpu's clock speed.  Do we 
setup two such loops, one for .89mhz, and another with more nops for 
1.78mhz?  And how about the 500kbyte modes?

Has anyone tried to invert the original order of sta & stb which might 
effect the timing enough to give the 1773 time to get it right too?
where

readloop lda $ff4b get a data byte
  stb $ff40 enable halt
  sta  ,x+ put it away
  bra readloop

This way the halt would be enabled a cycle earlier, or the read a cycle 
later, depending on how you look at it, but I'm not sure how one would 
handle the last byte on the nmi edge if the halt was fast eough to stop 
the storage cycle before the bra.

Who has the actual data for the WD-17xx chips, or does this data sheet in 
fact lie to us?  The only data sheet I have is on the MB8877 and its 
fairly terse.  And probably not at all applicable to the WD17xx stuff in 
matters such as this...

>When you change the read or write loops in this manner, the code no
>longer is dependent on odd/even bytes. The BLOB no longer is active.

-- 
Cheers, Gene
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