[Coco] [Color Computer] 1M simms in Cloud9 SIMM upgrade kit

[jdaggett at gate.net]

Mike

The GIME chip does a row only refresh (RAS). In that manner there 
is no need to refresh both row and col. In this manner the each 
individual row is addressed once every 15.6 uS. Then all 256 rows 
of the memory array is then refreshed every 4 mS. 256K drams 
require 256cylces every 4 mS refresh. So does the 64Kx4 drams  
used in the 128K x 8 configuration. 256K x4 and 1M x1 chips 
require 512 cycles every 8 mS. 

The memory  array for the Coco 3 is arranged  as 256 rows by 1024 
cols by 15 bits deep. That is the three deminsional memory array. 
To make one megabit drams to work is an extra bit has to be added 
to the refresh counter. Instead of cou nting to 256 it needs to be 
512. 

Now there maybe a way of using the RAS and CAS lines to 
demultiplex the Z-address bus and use static ram instead of 
dynamic ram. Then you do not  have to worry about refresh cylces 
or not. 

james

On 29 Jun 2005 at 9:08, Mike Pepe wrote:

To:             	ColorComputer at yahoogroups.com
From:           	Mike Pepe <lamune at doki-doki.net>
Date sent:      	Wed, 29 Jun 2005 09:08:55 -0400
Subject:        	Re: [Coco] [Color Computer] 1M simms in 
Cloud9 SIMM upgrade kit
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> Paul, Gene...
> 
> I think you're right. I see a flaw in my theory but practical testing
> seems to go with Paul on this one.
> 
> A 256k DRAM, although it's "9 bits per axis" actually only has 256
> columns (8 bit refresh)
> 
> A 1M DRAM, whichi is "10 bits per axis"  only has 512 columns (9 bit
> refresh)
> 
> I would still think that in theory you just don't use half of those
> columns and the memory works fine. I ran the cloud9 memory test for
> hours and hours and hours and everything tested fine.
> 
> I then ran the practical peripherals memory test just to verify  my
> results, and it reports errors with anything I test except 256k
> modules. So, it's possible the algorithm in the first memory test was
> keeping things refreshed but a more sophisticated test shows some
> errors.
> 
> It's too bad we can't hack that stupid GIME chip. there's plenty of
> time to refresh a 1M chip as although there are twice as many columns
> to refresh the time in which you have to refresh it is doubled.
> 
> Well it was an interesting experiment nonetheless!
> 
> Paul T. Barton wrote:
> > Mike,
> > 
> > Just let it sit for a minute or so,
> > doing nothing, it may crash. My experience.
> > 
> > Paul T Barton
> > 
> > 
> > --- Mike Pepe <lamune at doki-doki.net> wrote:
> > 
> > 
> >>I was going to send this over to Mark at cloud
> >>9, but I figured I'd open it to the group.
> >>
> >>I'm unsing a Cloud 9 512k SIMM upgrade board.
> > 
> > --snipped--
> > 
> >>Then I got brave and installed a set of 1M 3
> >>chip modules. They also 
> >>work! I've been running a memory test on it for
> >>several hours and no problems reported.
> > 
> > --snipped--
> > 
> > 
> > 
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