[Coco] [Color Computer] USB project

[James Diffendaffer]

--- In ColorComputer at yahoogroups.com, "James Diffendaffer"
<jdiffendaffer at y...> wrote:
> Given that fact, if I address it at FF70 the circuit looks like it can
> be implemented with a 12 input NAND gate, a quad 2 input NAND gate, a
> 3 to 8 decoder and a dual 4 input NOR gate.
> I need to double check that though.  

Ok, the 3 to 8 decoder is only required to add additional hardware or
switch the address above FF70-FF71 so I'm going to describe the
circuit without it. 

Total cost for address decoding and buss logic should be under $2. 
Probably under $1 if you don't buy the parts somewhere expensive.

The Cypress USB chip requires the following inputs:
D0-D7 for data I/O
A0 to select which address on the chip you will be accessing
/R read line active low
/W write line active low
/CS chip select active low

Attach the R/W line from the CoCo to both inputs of one gate on the
quad 2 input NAND.  This is an inverter and splits the R/W into
separate R and W lines.  I think R is active low on the CoCo so you
also connect the CoCo R/W line to /R on the Cypress chip and the
output from the NAND to the /W line on the Cypress chip.  If the read
is active high on the R/W line just reverse the connections on the
Cypress /R and /W lines.

D0-D7 on the CoCo are attached to D0-D7 on the Cypress chip
A0 on the CoCo is attached to A0 on the Cypress chip

A4-A6 and A8-A15 are attached to the inputs on the 12 input NAND gate
The unused input is tied high
The output of the NAND is connected to /CS on the Cypress chip
That takes care of the address lines that need to be high.

Now attach A1-A3 and A7 to the inputs on one of the gates on the NOR
chip.  Attach the output of that gate to the inputs of one of the
gates on the quad NAND.  Attach it's output to the /CS line on the
Cypress chip.  That takes care of the low address lines. 

Now that leaves an unused NOR gate and two unused inverters.  I need
to look at timing diagrams to see if I need to involve the CoCo clock
signals... which I probably will.  I should not need additional gates
to do so.

A0-A2 could have been attached to the 3 to 8 decoder to easily move
the address between FF00 and FF07.  The address can also be altered by
swapping around address lines between the 12 input NAND and the NOR
gates as long as there aren't more than 2 more high address lines (3
if I don't need to involve the clock) or 4 low address lines.

James, thanks for the VHDL.  I spent a half hour looking through
examples on the web and none did what I wanted.  They were either too
simple or "here is a complete CPU in VHDL".
That looks pretty simple so the CPLD project might not be so bad.
Really, I just need the proper examples to figure out VHDL.  I don't
have problems with the logic.
A VHDL version of USB interface just needs the extra pins defined, a
little logic and it's done.  Too simple.





------------------------ Yahoo! Groups Sponsor --------------------~--> 
<font face=arial size=-1><a href="http://us.ard.yahoo.com/SIG=12hn4ar84/M=362335.6886445.7839731.1510227/D=groups/S=1705005378:TM/Y=YAHOO/EXP=1122736140/A=2894361/R=0/SIG=13jmebhbo/*http://www.networkforgood.org/topics/education/digitaldivide/?source=YAHOO&cmpgn=GRP&RTP=http://groups.yahoo.com/">In low income neighborhoods, 84% do not own computers. At Network for Good, help bridge the Digital Divide!</a>.</font>
--------------------------------------------------------------------~-> 

Brought to you by the 6809, the 6803 and their cousins! 
Yahoo! Groups Links

<*> To visit your group on the web, go to:
    http://groups.yahoo.com/group/ColorComputer/

<*> To unsubscribe from this group, send an email to:
    ColorComputer-unsubscribe at yahoogroups.com

<*> Your use of Yahoo! Groups is subject to:
    http://docs.yahoo.com/info/terms/