[Coco] Fw: CoCo Hardware Questions

[jdaggett at gate.net]

Dino

FIrom your description I inferr that your either have a Coco1 or a Coco2. Both are 
near identical with minor differences.

Wtih that in mind here are a few basics

There are three main chips used in the Coco1 and 2 . They  are 

MC6809 the CPU
MC6847 the VDG
MC6883 the SAM chip 

The Sam chip provides the main crystal oscillator and key timing frequncies. They 
are the ECLK/QCLK and the Color Burst Frequency of 3.579MHz. The E and Q 
clocks are the main clocks for the CPU, MC6809E. The E clock also is provided to 
synchronize with the PIA chips, MC6821. From the SAM chip, the color burst 
frequency goes to the VDG chip and to the  MC1372 modulator chip. 

See below for the answers to your questions   

On 24 Jan 2005 at 21:56, Dino Steeman wrote:

From:           	"Dino Steeman" <dino at dds.nl>
To:             	<coco at maltedmedia.com>
Date sent:      	Mon, 24 Jan 2005 21:56:04 +0100
Subject:        	[Coco] Fw: CoCo Hardware Questions
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> * There is only an E-line going to the 6809 and not to the VDG. How
> does the VDG "know" when to access memory? Does the 'clock'-pin do the
> trick?
> 
The VDG accesses memory through the SAM chip. The CGD is sy nched to the 
SAM chip via the color burst frequency that is derived from the 14.318 MHz crystal 
oscillator in the SAM chip. Tha SAM Chip,  Synchronous Address Multiplexer,  
multiplexes the CPU address,  the video address and the refresh count to the dram 
chips via the z-buss. The video and MPU memory is shared in ascheme that is 
called IDMA, Interleaved Direct Memory Access. This is the main function of the 
SAM chip. To control access to the memory by the MPU and the VDG. 

All machine cycles start with the falling edge of the E clock. T he MPU, MC6809E 
reads data into it on the falling edge of the E clock. On the rising edge of the Q 
clock the MPU address is latched to the address bus for the next instruction. This is 
written to the SAM chip. While the E clock is low, the SAM knows that this is the 
VDG portion of the cycle. DUring that porttion the Z-buss has the VDG address on it 
and it reads the memory for data to display. When the E clock is high that is the 
MPU portion and the address that is written to the SAM chip is then paced on the Z-
buss and either data is read or written to memory depending on the state of the 
R/W* line.

> * What does the Q-signal do?
> 
The purpose of the Q clock is to provide a second clock internal to the MPU that is 
90degrees out of phase from the E clock. For the MPU the Q clock leads the E 
clock by 90 degrees. Some of the main timings that are generated with the Q clock 
is when the address is valid and when write data is valid. The MPU places the 
address of the next memory location on the address on the rising edge of the Q 
clock. On the falling edge of the Q clock and if the R/W* line is low then the data 
buss is latched with the data to write to that memory location. If the cycle is a read 
then the data from memory is latched in on the falling edge of the E clock. 
  
> * As the VDG is reading one byte at a time, and as it must manage to
> go through the entire videoram, is there a screen image stored
> anywhere for the video-signal? (I know, complex question, but
> still...)

The VDG has the ability to locate the block of video ram anywhere in the memory 
map but must reside on 512 byte boundaries. That is the starting address must be 
divisible by 512. This address is set by the seven bits programmed into  F0 to F6 
registers within the SAM chip. The VDG chip send a signal to the SAM chip to tell it 
to decrement/increment the address one byte at a time as needed. The video data 
read from memory is passed from ram to the SAM chip to the VDG chip through 
transparent latches. 

The VDG chip has timing generators that synchronize the display. It has all the 
timing generators for the composite sync and proper display on a raster screen. 

hope this helps 

james