[Coco] ceramics ...

[jdaggett at gate.net]

Mark/Kevin

The 6809 is HMOS procoss,  High Speed NMOS. That is to say that all the 
transistors on the IC are N type MOS devices. Unlike CMOS, Complementary MOS,  
which will have N and P type MOS transistors. The advantage at that time, 1980, 
was that NMOS was faster than CMOS but produced more heat due to larger 
switching currents. The ceramic package has a lower thermal resistance to heat 
than injection molded. Therefore the heat generated from the switching is removed 
from the die faster than in injection molded plastic devices. 

Motorola marks the mask set on each of the parts. This will be a three or four 
character string (D12A) on the same line as the date code. I have four different 
68x09E's that have four different date codes and four different mask sets. Back in 
1977 when the 6809  design was first started Motorola used 4 inch wafers to 
fabricate their ICs. In fact in 1999 they still had one wafer fab facility that used 4 
inch wafers fo rengineering runs. In the 80's the mos fab lines were all switched 
over to 6 in wafers and later in the 90's to 8 inch wafer. Every time Motorola 
changes the die, a new mask set is issued. This can be from a change in the wafer 
size, a shrink of the die, or even to change one of about 25 mask layers used in 
creatign an IC to correct a field issue. My guess is that one or more of the above 
were done. Originally the wafer process was done on 1 to 3 micron process. 

My guess is that during the 80's the die went under a shrink. Most likely a 75% or 
63% shrink and ended up with 0.75 micron process. Each time there is a die shrink 
the transistors get smaller. Smaller transistors use less current. By using less 
current the overall dissapation of heat the device is speced for, 1 W, can now be 
made using injection molded plastic. A cost savings of 3 to 5 cents per pin. At 40 
pins that is significant savings. Smaller die and larger wafers yield lower costs and 
more profit. Motorola started  in the mid 80's phasing out the ceramic package due 
to costs and improvements in wafer processing allowed injection molded plastic to 
meet the desired heat dissapation factors for many of their products that were in 
ceramic. 

As I stated before the main enemy to ICs is heat. Current drain generates heat. 
Increased clock speeds increases average current draw. Remove heat and up to a 
certain point, the specified maximum clock speed can safely be exceeded. There is 
a point to where even if the IC is cooled sufficiently that the design of the IC will not 
allow any faster clock speeds. On the 6809 that is most likely between 4 and 6 MHz 
buss speed. My best estimates are considering that the address mode decode logic 
uses at most four gates. Each gate has between 3 and 5 nS propogation delay. That 
would be pushing the internals of the processors at 6 MHZ. In honest, Even sith 
sufficeint heat sink the Motorola 6809 will most likley start to crap out between 4 
and 5 MHz. 3 to 3.5 is reliable with later mask set devices. IF the date code were 
say 1985 or earlier, 3 MHz maybe pushing them. Post 1990 date codes maybe 
capable of 4 MHz if kept cooled. 

One other note. The circuit and technigue that John K uses to bump up the clock 
speed during internal processing and then slow down for I/O is an excellent scheme. 
He pushes the interanls to 4 MHz and it might even work faster. The 6809e  parts 
are a bit more difficult to do that with but the 6809 parts have the pins to coordiante 
with slower peripheral devices. In doing that, the processor slows down to talk to the 
outside world. During that period the part does have a few milliseconds to cool off. 

There are formulas to calcuate the interal temperature based on the package heat 
resistivity and the external temperature. Also there is the factor of exchanging the 
heat from the heat sink to the ambient air.  The heat sink needs to be sufficiently 
large enough to remove the internal heat and dissipate it into the air surronding the 
IC.  The hotter the outside air is the larger the heat sink needs to be. 

You just can not slap a heat sink on and crank up the clock. You have to do a bit of 
math to calcualte the heat sink size. The major fault of over clocking is if the heat 
sink method failes the IC will die a death real fast. 

james



On 4 Sep 2004 at 16:45, Mark Marlette wrote:

Date sent:      	Sat, 04 Sep 2004 16:45:28 -0500
To:             	CoCoList for Color Computer Enthusiasts 
<coco at maltedmedia.com>
From:           	Mark Marlette <mmarlett at isd.net>
Subject:        	Re: [Coco] ceramics ...
Send reply to:  	CoCoList for Color Computer Enthusiasts 
<coco at maltedmedia.com>
	<mailto:coco-
request at maltedmedia.com?subject=unsubscribe>
	<mailto:coco-
request at maltedmedia.com?subject=subscribe>

> At 9/4/2004 12:01 PM -0700, you wrote:
> 
> Kevin,
> 
> Good question for james. I'm not sure why they had so many different
> grades with such little base clock speed difference if you could just
> add a heat sink to it and over clock it. ?????  This is exactly what I
> was referring to.
> 
> Mark
> 
> 
> 
> >Hi,
> >
> >         What kind of heat sinking? Were they ceramics?
> >
> >         Lets back up a bit. From what I know they sold 3 speed
> >         grades of 
> > the 6809:  6809 (1 MHz), 68A09 (1.5 MHz), and 68B09 (2.0 MHz). Are
> > these made different?
> >
> >                                   kevin
> >
> >jdaggett at gate.net wrote:
> >>Mark
> >>We used 68B09's at clock speeds of 12 MHz, 3 MHz buss speed 24/7 for
> >> months on end. Had little fail ure from that. Yes it is quite
> >>possible to operate an 8 MHz 68K at 14 MHz. Again it may be
> >>necessary to heat sink the chip though. james
> >
> >--
> >Coco mailing list
> >Coco at maltedmedia.com
> >http://five.pairlist.net/mailman/listinfo/coco
> 
> 
> 
> -- 
> Coco mailing list
> Coco at maltedmedia.com
> http://five.pairlist.net/mailman/listinfo/coco