[Coco] Interrupt Confusion

[Roger Taylor]

At 08:31 AM 1/12/2004 -0500, you wrote:
>Robert
>
>According to the databook I have the Control register is addressed
>when RS0 and RS1 are both high. It furthter states that bits 6 and 7
>of the control register are read only bits and are cleared with a read
>or a RESET. Can you then explain how this equates to an $xx02
>address? At $xx02 is the either the Data Direction Register or the
>Peripheral register depending on the state of bit 2 if the Control
>Register which is acessed at $xx03?
>
>james


When an interrupt occurs, the CR flag(s) will be set and will remain set 
until you clear them (by reading the PDR register, the even address below 
the CR).  Reading the CR flags does just that and nothing more.

You can check the BASIC IRQ servicing code to see proof of this.  I 
probably have the most descriptive 6821 PIA docs around, and I can't find a 
reference to this either.  Actually, it's probably in there, but there's so 
much that I can't easily locate it.  My docs cover all of the hardware 
aspects as well.  I've done so much PIA programming that most of this just 
comes naturally to me without having to resort to the specs.  However, 
there are so many other things possible with the PIAs that the CoCos never 
used, so it's nice to have a 6821 service guide to go by when you're doing 
PIA programming.


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Roger Taylor