[Coco] CoCo RGB video timing and levels

[jdaggett at gate.net]

Alex

Correct that the GIME reads from ram are based on a 3.579 MHz clock. That would 
not be the pixel clock. Instead the pixel clock would need to be 8 times the E-Clock 
in high speed mode and 16 times in low speed mode. This makes the pixel clock 
14.318MHz. In slow speed the GIME can make two reads from ram. Based on 
14.318 MHZ pixel clock and 640 pixel lines the GIME actually has about 912 pixels 
per line. That would mean about 144 pixels for sync, 640 pixels for display and 64 
pixels for the right and left borders.

I know that the borders are there on the monitor as you can see it in 80 character 
text mode. But 64 pixel border is over 10 characters wide border! Maybe it is.

A 14.28 MHz is rather difficult to obtain from a 28.6363 MHz crystal unless you use 
a fractional-n divider. Was that technology available then in the 1985/86 time 
frame? A fractional-n divider allows clock changes on the fly!

even still, I believe that 14.318 MHz is awfull high for a pixel clock for 640 pixel 
display. A value more like 12.56 MHz would be more reasonable. If the service 
manual is correct with 280 nS read from ram in the VDU cycle, even a 14.28 Mhz 
pixel clock is to fast. The 8th bit is shifted out before the next byte is read. It would 
seem that the pixel clock is a bit slower but I am uncertain as how the designer of th 
chip derived the clock frequency without a fractinal-n divider. 

james 

On 24 Aug 2004 at 15:54, Alex wrote:

From:           	Theodore (Alex) Evans <alxevans at concentric.net>
Subject:        	Re: [Coco] CoCo RGB video timing and levels
Date sent:      	Tue, 24 Aug 2004 15:54:16 -0700
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> 
> On Aug 24, 2004, at 10:36 AM, jdaggett at gate.net wrote:
> 
> > Looking at the Service manual, it looks as the if the GIME chip is
> > running a pixel clock of 3.579 MHz or 280nS. In 640x200 two color
> > mode, one read covers eight pixels and the VDU has to read every 8th
> > pixel or a total of 80 reads. In 640x200 4 color mode the VDU has to
> > read every 4th pixel and makes a total of 160 reads. Plenty of time
> > even at a buss rate of 1.78 MHz.
> 
> At 640x200 the GIME writes at a rate of 14.28 million pixels per
> second.  This certainly seems like a pixel clock of 14.28 MHz to me. 
> It reads from memory at a rate of 1.78 MHz  (16-bits at a time). 
> Neither one of these corresponds to a pixel clock of 3.579 MHz.  It is
> true that the CPU and video read cycles are interleaved and in fact
> the CoCo is quite capable of doing one of each every cycle.
> 
> -- 
> Theodore (Alex) Evans | 2B v ~2B = ?
> 
> 
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