[Coco] GIME questions

[mmarlett at isd.net]

Kevin,

What would be the ratio of unis to tres? Here at lab north, tres rule the
roost! :)

Mark
Cloud-9

>David,
>
>	Wouldn't it be simpler (and smarter) to do your testing
>on a deuce instead? It is a simpler beast with less ... other stuff
>to get in the way of your testing your cpu replacement. It is also
>easier to replace (deuce to tre ratio on EBay is at least 3 to 1).
>
>	Good luck with this project! This is a very innovative idea!
>
>					kevin
>
>Robert Gault wrote:
>> David Gacke wrote:
>> 
>>> Hi Robert,
>>>
>>> Sorry it wasn't clear. So far, you are correct though.  I am stepping
>>> thru the code with my dsPIC CPU that I'm coding, not a 6809 or 6309 and
>>> am trying to figure out what I broke.
>>>
>>> To try and put it simply, by looking at that startup code, what would
>>> make a shadow copy of what is located at C000 appear at 4000.
>>>
>>> Which GIME registers bits would I set if I wanted to do this
>>> intentionally?
>>>
>>> I've stepped thru the code and am not finding a broken instruction. I
>>> want to fully understand how to reproduce this intentionally, maybe
then
>>> I can figure out what is going wrong.
>>>
>>> This one has me a little bit stumped, especially since I've never
really
>>> done assembly on the CoCo (lots of other systems though), and I've
never
>>> twiddled the bits on the GIME before.
>>>
>>> Thanks very much for the assistance.
>>>
>>> Dave
>> 
>>  ><snip>
>> I think this will be what you want. I strongly advise you finding a link

>> to this service data and more before trying to recreate the GIME chip.
>> 
>> The service manual defines the GIME INIT0 register at $FF90 as follows
>> bit #    name            function
>> 7        COCO            1= Coco 1& 2 compatible
>> 6        M/P             1= MMU enabled
>> 5        IEN             1= Chip IRQ enabled
>> 4        FEN             1= Chip FIRQ enabled
>> 3        MC3             1= DRAM at XFEXX constant
>> 2        MC2             1= standard SCS  (ie. disk)
>> 1        MC1             ROM map
>> 0        MC0             ROM map
>> 
>> MC1   MC0           Mapping
>> 0      x             16K Internal, 16K External
>> 1      0             32K Internal
>> 1      1             32K External except for vectors
>> 
>> 
>
>
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