[Coco] MC4517 DRAM questions

[Patrick Ulland]

CPU only designs usually use static RAM to avoid this problem. Early 
video systems like CoCo got clever – video generation already involves 
scanning rows and cols in a timely manner, so the SAM, GIME, 
VIC(ducking)  handles that and the CPU gets a free ride. PCs went with a 
dedicated memory controller aka ‘North Bridge’ which has since been 
assimilated by ‘the motherboard chip’.

Handling refresh by yourself is going to be exactly that. The ZX80 and 
ZX81 are the only CPU driven DRAM examples I can think of.

You need a book, not an email. This intro helps: 
https://user.eng.umd.edu/~blj/talks/DRAM-Tutorial-isca2002.pdf




On 3/15/2023 5:22 AM, Richard Cavell via Coco wrote:
> I’ve found a datasheet here for the MC4517 DRAM chip: https://orchidsound.com/mcm4517p12-dram-16-384-bit-16k-x-1-120ns-pdip-16-motorola/
>
> I wonder if I’m reading the datasheet correctly.
>
> 1. Is it correct for me to consider that the 7 bit row ...
>
>