[Coco] VCC possible bug in 6309 & 6809 emulation and general Wally news!
Robert Gault
robert.gault at att.net
Mon Jun 11 20:18:48 EDT 2018
Richard Cavell wrote:
> What we really need is for someone to code a program that systematically tests this type of transfer, and run it on both real hardware and the emulators. Then bug report to any emulator that doesn’t produce the result that the real hardware arrives at.
>
><snip>
Well you can take this as an example but it should be tested by others. I don't get what Walter
stated about the Z register with VCC. The test was made by programming with EDTASM6309 on VCC 2.01b
set for the 6309 cpu.
START LDA #4
TFR $1F,$8C *i.e. TFR A,Z
TFR $1F,$C8 *i.e. TFR Z,A
SWI
END
Now this should place 4 into regZ and then put 4 back into regA if Walter is correct about a bug in
VCC. However, regA became zero so regZ must have been reset/kept as 0.
I don't see any way to read regZ directly.
What is interesting is that in ZBUG and stepping through the code, you get:
LDA #4
TFR A,?
TFR ?,A
SWI
This code also works correctly in MESS .158 with 6309 emulation.
With unequal transfers on the VCC:
START LDA #4
FCB $1F,%10000001 *I.E. TFR A,X
SWI
END
regA=4 regX=$FFFF
That is not ignored but is not what should happen. The same code with MESS .158 gives
regA=4 regX=$0404
That is what the 6x09 .pdf says should happen.
Similarly with:
MESS .158 VCC 2.01b
START LDX #4
FCB $1F,%11000 *I.E. TFR X,A
SWI
END
regX=4 regA=0 regB=0 regX=4 regA=$FF regB=0
START LDX #4
FCB $1F,%11001 *I.E. TFR X,B
SWI
END
regX=4 regA=0 regB=4 regX=4 regA=0 regB=FF
START LDX #$400
FCB $1F,%11000 *I.E. TFR X,A
SWI
END
regX=0400 regA=4 regB=0 regX=0400 regA=FF regB=0
START LDX #4
FCB $1F,%11001 *I.E. TFR X,B
SWI
END
regX=0400 regA=0 regB=0 regX=0400 regA=0 regB=FF
A real 6309 Coco3 gives the same results as MESS.
I've not tested all TFR possibilities as I probably would not use this type of programming. :)
Robert
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