[Coco] Optimizing 6809 Assembly Code: Part 2 – Speedup Storing Data – Unrolling Loops

[Dave Philipsen]

Wow, this is making me think I should do some research on the CoCo3FPGA.  The long-standing version with John Kent's 6809 core is not 100% cycle accurate to the real 6809 and it generally runs a little faster. It would be good to have a chart with cycle counts on all of the instructions.  Of course there is less need to optimize for speed when the processor is running at 25 MHz.

Dave

> On Sep 17, 2017, at 1:51 PM, L. Curtis Boyle <curtisboyle at sasktel.net> wrote:
> 
> Glen - any thoughts of doing a followup with similar tips on 6309 specific things? Since the cycle counts do change (for example, tfr is only 4 cycles in 6309 native mode), and there are some things that are not obvious (like using W as an index register or offset to an index register is faster than any other register), etc.?
> 
> L. Curtis Boyle
> curtisboyle at sasktel.net
> 
> 
> 
>> On Sep 17, 2017, at 9:03 AM, Glen Hewlett <glen.hewlett at sympatico.ca> wrote:
>> 
>> Hi Mark,
>> 
>> I love to hear stuff like this!  That’s the main reason I posted the blog.  Of course it’s also a great reference for me to also refer to… :)g
>> 
>> Yeah, I hear you about keeping things the same at first, then optimized later.  Very important.
>> 
>> Cheers,
>> Glen
>> 
>>> On Sep 17, 2017, at 8:15 AM, Mark McDougall <msmcdoug at iinet.net.au> wrote:
>>> 
>>> Hi Glen,
>>> 
>>> Great series of articles!
>>> 
>>> Wasn't aware of the tfr/leau optimsiation - although I did note that tfr was _slow_! Just went through Knight Lore (some news on that subject very soon) and replaced 14 occurrences - thanks!
>>> 
>>> It also reminded me to look for bsr,rts and I found a few of those as well but in my defence, I was focused at the time on keeping the code "the same" as the original! ;)
>>> 
>>> Regards,
>>> 
>>> -- 
>>> Mark McDougall
>>> <http://retroports.blogspot.com.au>
>>> 
> 
> 
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