[Coco] Fwd: Re: FPGA VS Software Emulators

[Mark McDougall]

On 26/07/2017 3:15 PM, Dave Philipsen wrote:

> Also, there are a lot of websites out there that will give you VHDL (and 
> Verilog) examples and syntax.  Since I started with VHDL I have not yet 
> delved into Verilog much but as I understand it you can pretty much do 
> anything with either language. I believe VHDL is the preferred language 
> in Europe and Australia whereas Verilog is more where many US developers 
> are focused.

The VHDL vs Verilog debate is basically a 'religious' thing and there's 
nothing you can't achieve in both languages.

You're most likely to stick with the one you started with, unless you 
really have trouble wrapping your head around it and the alternative 
comes more naturally to you. As Dave says, the _syntax_ for Verilog is 
more C-like, but don't expect C code to work! ;) The concepts in both 
(VHDL & Verilog) are similar.

Personally, I started with VHDL but spent about 6 intense months working 
in Verilog on a huge testbench - code used for testing that was never 
going to be synthesized in a device - so I've got a decent handle on 
both. I've also had to incorporate Verilog components into my (VHDL) 
designs - yes you can mix and match. I prefer VHDL for writing code to 
be synthesized, and Verilog for writing testbenches!

A cheap way to start is using a simulator; you can see your signal 
waveforms graphically and it's much easier to experiment and debug. If 
I'm writing a complex self-contained module I generally simulate it 
first in a simple testbench.

Regards,

-- 
Mark McDougall
<http://retroports.blogspot.com.au>