[Coco] FPGA VS Software Emulators

[Leslie Ayling]

Hi Walter, et al

>> At it's current top speed of 25MHz, that represents a 40ns cycle 
>> time.
>> Each cycle has a potential CPU and VIDEO access to the SRAMS, so the 
>> SRAMS are being accessed at no faster than 20ns at present.

> So to me it sounds as if the emulated CPU and GIME are functioning 
> like real separate physical devices that require interleaving to the 
> memory.

That is correct, in the coco3fpga design anyway.
I don't know if the "coco on chip" source code is available for perusal 
anywhere to confirm if it works the same way?

> That’s amazing!
> So even though there is just one FPGA unit the emulated CPU and the 
> emulated GIME(GPU)  both behave as two separate devices!
> So they must run in parallel!
> I'll say it again, that's amazing!

> How much parallelism can occur in these FPGA devices?

Limited only by the resources in the particular FPGA chip you are using.
You will always have finite amounts of logic resources, inter-connecting 
signal pathways, global clock routing, clock generation blocks and so 
on.

Current coco3fpga design uses:
Logic: 62%
Pins: 89%
Memory Bits: 49%
of the available resources on the Terasic DE1 board (Cyclone 2 - 2C20)

> I suppose the down side is the maximum speed of the memory accesses 
> will only be half as fast of what they could be!

No different to a "real" 6809 :)

> Walter

Leslie