[Coco] FPGA VS Software Emulators

[Scott Wendt]

Many times the speed is limited by the logic design of the processor itself. Propagation delays, signal stabilization time requirements and other things I didn't stay in my EE degree long enough to learn about. Modern fast designs aren't just old designs on a faster substrate but actually designs made to go that fast in the first place.

________________________________
From: Coco <coco-bounces at maltedmedia.com> on behalf of Walter Zambotti <zambotti at iinet.net.au>
Sent: Tuesday, July 25, 2017 7:03:53 PM
To: 'CoCoList for Color Computer Enthusiasts'
Subject: Re: [Coco] FPGA VS Software Emulators

Mark

>So the input clock bears little hint as to the rate things are happening inside your device. eg the >above-mentioned examples with a 50MHz clock are actually running quite slowly (~25MHz) inside. >Contrast that with a design I've worked on with a 24MHz input clock; running logic at 150MHz and >DRAM at 4-500MHz...

And the reason we can't use that same kind of trick for the CoCo FPGA projects is....?

Walter

-----Original Message-----
From: Coco [mailto:coco-bounces at maltedmedia.com] On Behalf Of Mark McDougall
Sent: Wednesday, 26 July 2017 8:46 AM
To: coco at maltedmedia.com
Subject: Re: [Coco] FPGA VS Software Emulators

On 26/07/2017 10:30 AM, Mark McDougall wrote:

>> Cyclone® IV EP4CE22F17C6N FPGA
>> runs at 50 MHz.
>> Altera Cyclone II 2C20 FPGA
>> runs at 50 MHz.

For those interested, the input clock to an FPGA is usually chosen with regards to the desired clock frequencies inside the design. By using multipliers and dividers FPGA PPLs have limits on the resolution of generated frequencies, so if you have a particularly critical frequency you need then you'd better make sure your input clock is a "nice"
frequency. There are even further constraints when generating multiple frequencies from the one PLL (input clock), which is often the case, and more-so again in smaller devices.

Often parts of your design that don't have a specific frequency requirement will run at a "convenient" frequency based on what the PLL can output.

So the input clock bears little hint as to the rate things are happening inside your device. eg the above-mentioned examples with a 50MHz clock are actually running quite slowly (~25MHz) inside. Contrast that with a design I've worked on with a 24MHz input clock; running logic at 150MHz and DRAM at 4-500MHz...

Regards,

--
Mark McDougall
<http://retroports.blogspot.com.au>

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