[Coco] Bad memory reported by Disto Coco III RAM Test by Tony Distefano

[Richard Goedeken]

I would suggest running my RAM test program:

http://www.fascinationsoftware.com/media/Coco3_RAM_Test_v1.2.zip

It will run continuously and print multiple errors, and give you the values
written and read back, so you may see a pattern.

Richard


On 11/16/2016 09:25 AM, Kip Koon wrote:
> Hi Michael,
> Whenever a 512KB memory upgrade is installed in the Coco 3, the original 4 memory chips are removed and C65 & C66 are removed by cutting one leg and lifting up on the cap slightly.  That's the procedure I used when I added my 512KB memory board to my Coco 3. That upgraded Coco 3 is still running strong.  
> As to the 8K address range that is bad, if an address line is truly bad, that 8K block would be bad everywhere, not just in one place I would think.  Maybe there is a logic problem somewhere maybe?
> Can anyone shed more light on this situation?
>
> Kip Koon
> computerdoc at sc.rr.com
> http://www.cocopedia.com/wiki/index.php/Kip_Koon
>
>
>> -----Original Message-----
>> From: Coco [mailto:coco-bounces at maltedmedia.com] On Behalf Of Michael R. Furman
>> Sent: Wednesday, November 16, 2016 11:37 AM
>> To: coco at maltedmedia.com
>> Subject: [Coco] Bad memory reported by Disto Coco III RAM Test by Tony Distefano
>>
>> Does anyone have a manual for the Disto Coco III RAM Test by Tony Distefano?
>>
>> http://www.colorcomputerarchive.com/coco/Disks/Utilities/Disto%20Coco%203%20RAM%20Test%20%28Tony%20Distefano%29%2
>> 0%28Coco%203%29.zip
>>
>>  I ran it on one of my Coco 3’s and it is returning an error, says that block 60 is bad, which I interpret to be 0x78000 to 0x79FFF
>>
>> A second observation is that when loading certain programs in to BASIC from the CocoSDC those programs get corrupted at the same
>> place every time.
>>
>> I was looking at the schematics to try to figure this out and I am a bit confused.  What I see on the schematic is each of the 256k x 1
>> chips on the 512 ram expansion board is attached to one data line and there are two sets of chips selected by WE0 or WE1.  The part I
>> am confused about is what it means that a particular range of memory is bad.  If one data bit is bad across the entire 256k range I
>> understand that one, that’s a bad chip. But it only seems to be bad in a particular 8k range of addresses, so maybe this is some issue
>> with RAS or CAS or a flakey address line to only the WE1 set of chips?
>>
>> What would happen if C65 or C66 still in place?  Why do they have those RC filters on RAS and CAS anyway?
>>
>> —
>>  Michael R. Furman
>> Email: n6il at ocs.net
>> Phone: +1 (408) 480-5865
>>
>>
>>
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>