[Coco] ROM Cart registers

[RETRO Innovations]

On 2/1/2016 12:32 AM, Darren A wrote:
> On Sun, Jan 31, 2016 at 8:46 PM, RETRO Innovations wrote:
>
>> Darren,
>>
>> Given Mark's explanation for how the sIDE strobes SLENB for SCS
>> addresses(I assume only those in the 16 bytes that it requires in the
>> memory map), does CocoSDC do the same for $ff4x addresses so that the SDC
>> will be available at all times, no matter the state of $ff7f on an
>> MPI-based system?
>>
>> Wondering, trying to determine how many Coco peripherals do this and how
>> many addresses in the address space are left for other things.
>>
>>
> The CoCo SDC only responds when SCS* is asserted. This is necessary to
> allow the CoCo SDC and a floppy controller to co-exist in an MPI since they
> both use the same addresses. The software (SDC-DOS and the Nitros9 driver
> for SDC) handle selecting and restoring the active MPI slot.
>
> I am surprised that the SuperIDE would assert SLENB* for addresses that are
> in the SCS range. It prevents any other device from using those addresses
> in a co-operative fashion as the MPI allows. I can't think of a reason why
> that would be needed except to ensure that the device is always active
> without having to manage MPI slot selection in software.
>
> If Mark has a different reason, I would be curious to know what it is.
>
> - Darren
>
Does anyone have a glenside ide controller schematic (google sent me to 
defunct links) I can check?  Maybe Mark is emulating some behavior that 
Jim Hathaway put in the original IDE controller.

I thought about shifting the registers up a byte to start at $ff59, but 
it appears the sIDE high byte IDE latch at $ffx8 is mirrored to 
locations $ffxa-$ffxf.

Jim


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