[Coco] 6809 FPGA Success

[Bill Nobel]

Hey Mark,  Thanks for the pointers.  I am using Grant’s code as is, just changed the pin assignments for the Nano.  Looking at his clock code I can’t tell if he has a POR established.  I just did a search on internet and found a few different ways it can be done.  I have to check into these machine states that Altera has on the chips.  I just found that out as I did the search.  I will be looking at the reports more closely, as the searches gave me clues on where to look for power up states.

Bill Nobel

> On Sep 29, 2015, at 6:11 AM, Mark McDougall <msmcdoug at iinet.net.au> wrote:
> 
> On 29/09/2015 12:59 PM, Bill Nobel wrote:
> 
>> Most of the time when I program the Nano, I get a flaky VGA, it flashes
>> the image in and out.  When i get the image I can see what I typed, but
>> very unstable display, until I get a good programming that boots
>> properly.
> 
> FPGA (ALtera Cyclone) bitstream packets are protected with CRC so it's very highly unlikely that the device is being configured with a corrupt bitstream, regardless of underlying OS layers.
> 
> Not knowing anything about your design, I would actually suspect it could be an issue with your start-up logic. Are you generating a POR (power-on-reset) in your design and holding that for several hundred clocks (at least) to reset all the elements of your design?
> 
> Regards,
> 
> -- 
> |              Mark McDougall                | "Electrical Engineers do it
> |  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"
> 
> -- 
> Coco mailing list
> Coco at maltedmedia.com
> https://pairlist5.pair.net/mailman/listinfo/coco