[Coco] 4 Port MPI PCB artwork (so far)

[RETRO Innovations]

 > Interface electronics are in the CPLD?


All but the buffers, which are separate on the smaller board.



 > Production real estate decisions. :) Probably based on what the board
 > houses need to fit max number up on their bigger starting sheets. OTOH,
 > they are probably pretty good at putting somebody else's job's on the
 > remaining 3" of width left over from your order. Might not hurt to ask
 > them how that works.


The houses I use don't care (they run large boards, and panelize these), 
but you pay by the sq inch, so any trimming that makes sense is a good 
thing.


 >
 > > I came up with a potential idea for a cheap 8 slot unit, using the
 > > last remaining IO pin on the CPLD and the fact that I will probably
 > > use IDE cables for the cabling. It might be possible to "daisy chain"
 > > 2 4 port MPI main units, and just set a jumper on one to be the
 > > "second 4", or "slave" if you like IDE parlance. Something I am
 > > kicking around, as it would not require building a new PCB, just
 > > repurposing the existing one.
 >
 > That seems like it would bring up a cable routing problem, unless a
 > series connection scheme was used. I think, its too early for my
 > thinker, no caffeine yet either. :( Adding a card edge pattern to the
 > far end, with a separate stacking connector pair, with 2 card edge
 > sockets of suitable width to do a 180 degree turnaround so the second
 > one is stacked, bottom to bottom & headed back the other way, or maybe a
 > wide dual row header & a short cable to make the turn around? The
 > cable, with IDC sockets crimped on would give more flexability. That
 > would have carts sticking out front and rear. Dunno. Just throwing it
 > out to see if it sticks. :)

The problem is the "interface".  The CPLD I am using has no more IO, so 
I have two options:


  * redo the CPLD pinout to free up some pins.  The design needs 4 pins
    per port (LED, SCS, CTS,CART) and 1 more pin for the selector switch
    (so, log2(number of ports)-2).  I can remove 7 by using the trick
    that the original MPI used (Use some TTL to note when $ffxx is being
    accessed, and then just run that 1 signal line into the CPLD), but
    it requires a TTL IC ($$), and that only buys you 7 lines, and you
    need 17.  You can free up some more by adding the multiplexors on
    the board, and that reduces the 32 pins for all 8 lines (4 per slot)
    to 3*4 (using a binary selector attached to some decoders like on
    the original MPI), but then you can't add logic to have more than 1
    slot on at a time for SCS, for example, and the TTL costs more money
    as well, which eliminates the reason to use the smaller CPLD.
  * Use a larger CPLD (TQ100 is the next choice, but it's more
    expensive, but then again, so is doing all of the above)


But, if you were able to run two MPis side by side, and have one only 
respond to the CTS and SCS configurations where $$ff7f bits 6 and 2 are 
1, then I think you get most of the neat features at a minimal cost.


 >
 > What SW are you using to do this? Apparently its a bit easier to use
 > than eagle, and this of course is too big for the free eagle.


I use EAGLE a *LOT*, for work.


EAGLE has it's idiosyncrasies, but I am very proficient at it. I have 
tried KiCAD and gEDA, but EAGLE is easier to use for me.

Jim