[Coco] FPGA 6809
Dave Philipsen
dave at davebiz.com
Mon Aug 31 12:58:27 EDT 2015
FWIW, I am playing around with a little tiny WiFi card that I bought
from China. It TCP/IP over wifi via RS232. I set up one board on a PC
and talked to it using hyperterminal and the other board on my DE1 with
the MultiComp project installed and a quick and dirty terminal program
and I was able to communicate between the two over my wifi network. I
also tested making some http GET requests and was able to pull down some
webpages from the internet. The really cool thing is that the card only
costs about 2 bucks.
Dave Philipsen
On , Bill Nobel wrote:
> I definitely agree with the Nitros9 part, as I am part of the
> creators. I am so looking forward to SD card and possible TCP/IP via
> RS-232 (beyond DriveWire).
>
> Bill Nobel
>
>> On Aug 30, 2015, at 11:41 PM, Dave Philipsen <dave at davebiz.com> wrote:
>>
>> I have not yet seen Roger's project. Does he have a website? I
>> definitely like what Gary has done on the DE1. To me there is nothing
>> like having a standalone little 6809 computer that can run NitrOS9 at
>> 25 MHz! Gary just released a new version with support for SD cards
>> and I'm working on getting it to boot OS9 from the SD card with some
>> software that will allow me to create partitions on the SD card.
>> Drivewire is a nice concept but for some reason I just can't warm up
>> to the idea of having to have a PC running next to my OS9 computer.
>> It's great for printing or accessing the internet I guess but I really
>> like the fact that we're getting really close to having a relatively
>> fast little computer that boots NitrOS9 on its own, requires very
>> little power, and has plenty of on-board storage capability.
>>
>> Dave Philipsen
>>
>>
>> On 8/31/2015 12:19 AM, Bill Nobel wrote:
>>> That is correct. I would like to achieve various 6809 systems (the
>>> main being a Coco). Yes Roger & Gary Becker have their projects
>>> going (I prefer Gary’s better) I tried taking Grant’s code direct to
>>> De0 with pin re-assingment. This didn’t work under newest versions of
>>> Quartus, so I have been trying to fix the varieties for my own
>>> sentiment. Once I have them working Everyone gets.
>>>
>>> Bill Nobel
>>>
>>>> On Aug 30, 2015, at 10:58 PM, Dave Philipsen <dave at davebiz.com>
>>>> wrote:
>>>>
>>>> Interesting. So when you are speaking in terms of "bdf" does that
>>>> mean you are actually drawing a schematic for your implementation?
>>>>
>>>> Dave
>>>>
>>>>
>>>> On 8/30/2015 11:52 PM, Bill Nobel wrote:
>>>>> Exactly what I am talking about David. Grant defines his CS lines
>>>>> in code vs .bdf (or symbols) My knowledge of FPGA’s is in schematic
>>>>> form.
>>>>>
>>>>> Bill Nobel
>>>>>
>>>>>> On Aug 30, 2015, at 10:46 PM, Dave Philipsen <dave at davebiz.com>
>>>>>> wrote:
>>>>>>
>>>>>> Actually, I stand corrected. Grant doesn't actually "marry" the
>>>>>> buses in his project and he explains why on his website:
>>>>>>
>>>>>> Similarly, all these CPUs have an 8-bit data bus. For the discrete
>>>>>> components, the data bus is bidirectional. This could have been
>>>>>> implemented in VHDL as bidirectional to match. However, the VHDL
>>>>>> components (including RAM and ROM) tend to have separate incoming
>>>>>> and outgoing data buses - this makes it easier to interface.
>>>>>> Therefore the 8-bit data bus found on a CPU is represented as two
>>>>>> separate data buses and are connected to the two data buses on the
>>>>>> breadboard.
>>>>>>
>>>>>> eg
>>>>>> di => cpuDataIn,
>>>>>> do => cpuDataOut
>>>>>>
>>>>>>
>>>>>>
>>>>>> This code in Multicomp attaches the different peripherals to the
>>>>>> CPU read data bus when the respective chip select goes low:
>>>>>>
>>>>>> cpuDataIn <=
>>>>>> interface1DataOut when n_interface1CS = '0' else
>>>>>> interface2DataOut when n_interface2CS = '0' else
>>>>>> sdCardDataOut when n_sdCardCS = '0' else
>>>>>> basRomData when n_basRomCS = '0' else
>>>>>> internalRam1DataOut when n_internalRam1CS= '0' else
>>>>>> sramData when n_externalRamCS= '0' else
>>>>>> x"FF";
>>>>>>
>>>>>>
>>>>>> An example of connecting the CPU write data bus to an external RAM
>>>>>> chip is found here:
>>>>>>
>>>>>> sramAddress(15 downto 0) <= cpuAddress(15 downto 0);
>>>>>> sramData <= cpuDataOut when n_WR='0' else (others => 'Z');
>>>>>> n_sRamWE <= n_memWR;
>>>>>> n_sRamOE <= n_memRD;
>>>>>> n_sRamCS <= n_externalRamCS;
>>>>>>
>>>>>> This is the way he keeps it flexible in order to work with both
>>>>>> the "internal" VHDL devices which may use separate data buses as
>>>>>> well as the real external devices that normally use a single
>>>>>> bi-directional bus. Additionally, there are some physical devices
>>>>>> which do not require the chip select to be active in order to
>>>>>> perform a write operation.
>>>>>>
>>>>>> Dave Philipsen
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> On 8/30/2015 10:42 PM, Bill Nobel wrote:
>>>>>>> I have gone over Grants code extensively and I never found a
>>>>>>> symbol file for Chip select. I see the CS lines defined, but not
>>>>>>> such as Roger’s define for a symbol file.
>>>>>>>
>>>>>>> Bill Nobel
>>>>>>>
>>>>>>>> On Aug 30, 2015, at 9:23 PM, Dave Philipsen <dave at davebiz.com>
>>>>>>>> wrote:
>>>>>>>>
>>>>>>>> If you take a look at the VHDL code in Grant Searle's Multicomp
>>>>>>>> project you'll find an example of this too.
>>>>>>>>
>>>>>>>> Dave Philipsen
>>>>>>>>
>>>>>>>>
>>>>>>>> On 8/30/2015 8:53 PM, Bill Nobel wrote:
>>>>>>>>> I have to post this here, A HUGE shout out to Roger Taylor for
>>>>>>>>> directing me in the right direction for the bus marriage on the
>>>>>>>>> FPGA versions of the 6809. I am a noob when it comes to these
>>>>>>>>> things and was having trouble marrying the data_in data_out
>>>>>>>>> busses together to form a actual bi-directional bus. I thought
>>>>>>>>> I was needing to build a circuit with latches/buffers, and he
>>>>>>>>> decides to give me a ~20 line piece of vhdl code that does the
>>>>>>>>> whole works based on Chip selects. Woo hoo….
>>>>>>>>>
>>>>>>>>> Bill Nobel
>>>>>>>>>
>>>>>>>>>
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