[Coco] FPGA 6809

Mon Aug 31 02:19:11 EDT 2015

No, you don't need to mess with PLLs but as I recall there is a virtual 
pin which must be correctly defined.  If you're not getting any activity 
maybe you need to look at where the 25 MHz clock is going....that might 
be your problem.  Also, the reset pin for the 6809 core is critical.  
Tomorrow I'll look at what I did on the DE1 (I haven't got it at home 
right now) and that might help you.  I can't see any reason why you 
shouldn't be able to get Multicomp running and even an SD card (if 
somebody like Gary publishes the Verilog code for the SPI) on the DE0.

Dave Philipsen

On 8/31/2015 1:04 AM, Bill Nobel wrote:
> So far, no.  I know I have to do the pin re-assingments, as of now I didn’t choose to use the fitter pins that Quartus suggested. Also, I still get a clock warning, Do I need to define a PLL?
>
> Bill Nobel
>
>> On Aug 30, 2015, at 11:55 PM, Dave Philipsen <dave at davebiz.com> wrote:
>>
>> The way I got it working initially was to use just the very basic design with minimal external components.  Initially, I did not wire up the external RAM chip. And even before you get the "ROM" working you can see the VGA signal come to life on a 'scope or even if you have a VGA monitor hooked up you usually can tell when it is sending a black signal and displaying a blinking cursor.
>>
>> Have you been able to get any kind of activity whatsoever out of the DE0-nano with Grant's Multicomp?
>>
>> Dave Philipsen
>>
>>
>> On 8/31/2015 12:37 AM, Bill Nobel wrote:
>>> No, I am porting to a DE0-Nano EP4CE2217C6N.  So far I only have ~1900 LE’s used.
>>>
>>> Bill Nobel
>>>
>>>> On Aug 30, 2015, at 11:30 PM, Dave Philipsen <dave at davebiz.com> wrote:
>>>>
>>>> So do you have one of the EP2C5 boards that Grant uses?  I bought a couple of them off eBay for around 16 bucks ea. including shipping from China.  Then I bought a couple of EP4CE10 boards from another company for around 32 bucks apiece and I was able to port over Grant's code pretty much by just re-assigning the pins.  It was also the same case with the Terasic DE1.  So I've got the Multicomp 6809 running on three different platforms.  At some point I'll publish some changes I made to Grant's code.  For one thing I added an MMU that is functionally identical to the CoCo 3 MMU so that hopefully it won't take much to get NitrOS9 Level 2 running on it.  I'm not looking to have all of the fancy graphics windows and stuff nor do I even need multiple windows.  One of the things I like about Grant's implementation is the VGA/CGA implementation.  It's nice to have some of those IBM line graphics characters in the character set.
>>>>
>>>> Dave Philipsen
>>>>
>>>>
>>>> On 8/31/2015 12:19 AM, Bill Nobel wrote:
>>>>> That is correct.  I would like to achieve various 6809 systems (the main being a Coco).  Yes Roger & Gary Becker have their projects going (I prefer Gary’s better) I tried taking Grant’s code direct to De0 with pin re-assingment. This didn’t work under newest versions of Quartus, so I have been trying to fix the varieties for my own sentiment.  Once I have them working Everyone gets.
>>>>>
>>>>> Bill Nobel
>>>>>
>>>>>> On Aug 30, 2015, at 10:58 PM, Dave Philipsen <dave at davebiz.com> wrote:
>>>>>>
>>>>>> Interesting.  So when you are speaking in terms of "bdf" does that mean you are actually drawing a schematic for your implementation?
>>>>>>
>>>>>> Dave
>>>>>>
>>>>>>
>>>>>> On 8/30/2015 11:52 PM, Bill Nobel wrote:
>>>>>>> Exactly what I am talking about David.  Grant defines his CS lines in code vs .bdf (or symbols) My knowledge of FPGA’s is in schematic form.
>>>>>>>
>>>>>>> Bill Nobel
>>>>>>>
>>>>>>>> On Aug 30, 2015, at 10:46 PM, Dave Philipsen <dave at davebiz.com> wrote:
>>>>>>>>
>>>>>>>> Actually, I stand corrected.  Grant doesn't actually "marry" the buses in his project and he explains why on his website:
>>>>>>>>
>>>>>>>> Similarly, all these CPUs have an 8-bit data bus. For the discrete components, the data bus is bidirectional. This could have been implemented in VHDL as bidirectional to match. However, the VHDL components (including RAM and ROM) tend to have separate incoming and outgoing data buses - this makes it easier to interface. Therefore the 8-bit data bus found on a CPU is represented as two separate data buses and are connected to the two data buses on the breadboard.
>>>>>>>>
>>>>>>>> eg
>>>>>>>> di => cpuDataIn,
>>>>>>>> do => cpuDataOut
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> This code in Multicomp attaches the different peripherals to the CPU read data bus when the respective chip select goes low:
>>>>>>>>
>>>>>>>> cpuDataIn <=
>>>>>>>> interface1DataOut when n_interface1CS = '0' else
>>>>>>>> interface2DataOut when n_interface2CS = '0' else
>>>>>>>> sdCardDataOut when n_sdCardCS = '0' else
>>>>>>>> basRomData when n_basRomCS = '0' else
>>>>>>>> internalRam1DataOut when n_internalRam1CS= '0' else
>>>>>>>> sramData when n_externalRamCS= '0' else
>>>>>>>> x"FF";
>>>>>>>>
>>>>>>>>
>>>>>>>> An example of connecting the CPU write data bus to an external RAM chip is found here:
>>>>>>>>
>>>>>>>> sramAddress(15 downto 0) <= cpuAddress(15 downto 0);
>>>>>>>> sramData <= cpuDataOut when n_WR='0' else (others => 'Z');
>>>>>>>> n_sRamWE <= n_memWR;
>>>>>>>> n_sRamOE <= n_memRD;
>>>>>>>> n_sRamCS <= n_externalRamCS;
>>>>>>>>
>>>>>>>> This is the way he keeps it flexible in order to work with both the "internal" VHDL devices which may use separate data buses as well as the real external devices that normally use a single bi-directional bus.  Additionally, there are some physical devices which do not require the chip select to be active in order to perform a write operation.
>>>>>>>>
>>>>>>>> Dave Philipsen
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On 8/30/2015 10:42 PM, Bill Nobel wrote:
>>>>>>>>> I have gone over Grants code extensively and I never found a symbol file for Chip select. I see the CS lines defined, but not such as Roger’s define for a symbol file.
>>>>>>>>>
>>>>>>>>> Bill Nobel
>>>>>>>>>
>>>>>>>>>> On Aug 30, 2015, at 9:23 PM, Dave Philipsen <dave at davebiz.com> wrote:
>>>>>>>>>>
>>>>>>>>>> If you take a look at the VHDL code in Grant Searle's Multicomp project you'll find an example of this too.
>>>>>>>>>>
>>>>>>>>>> Dave Philipsen
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> On 8/30/2015 8:53 PM, Bill Nobel wrote:
>>>>>>>>>>> I have to post this here,  A HUGE shout out to Roger Taylor for directing me in the right direction for the bus marriage on the FPGA versions of the 6809.  I am a noob when it comes to these things and was having trouble marrying the data_in data_out busses together to form a actual bi-directional bus.  I thought I was needing to build a circuit with latches/buffers, and he decides to give me a ~20 line piece of vhdl code that does the whole works based on Chip selects. Woo hoo….
>>>>>>>>>>>
>>>>>>>>>>> Bill Nobel
>>>>>>>>>>>
>>>>>>>>>>>
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