[Coco] Multi-Processor 6809 Computer System

[Theodore (Alex) Evans]

On 13-05-01 08:34 AM, Luis Antoniosi (CoCoDemus) wrote:

> Not a computer engineer expert but IFAIK only scalar architectures can
> achieve 1 cycle per instruction by pre-fetching and pipelining instructions
> and predicting branches. But on a coco machine what would be smaller cycle
> count ? 4 cycles ?

That isn't exactly true.  If you look at the first generation SPARC 
designs, they are scalar, but do not have any branch prediction.  They 
also have very shallow pipelines.  Of course one consequence of this is 
that the first instruction after a branch is executed whether the branch 
is taken or not.

In any case when in native mode a 6309 comes pretty close to taking a 
single cycle per byte fetched or written to memory (obviously there are 
a few exceptions) as a result, in order to be significantly faster with 
most code, a plug in replacement would have to implement some kind of 
caching scheme (probably impractical).

-- 
Theodore (Alex) Evans