[Coco] FW: Multi-Processor 6809 Computer System

[Kip Koon]

Mark,
That is very interesting.  Would you be able to share with our group your
design as a study aid?  I for one would like to see what you did.  
It is beginning to sound me that there is more than one way to create a
multi-core 6809 computer.  I am envisioning a system with expansion
capabilities to allow the user/creator/builder to  use as many slave 6809
boards as needed as one possibility, but the FPGA idea seems a lot better.
The speed increases could be substantial!  
Let's all get together sometime on Skype and pass around some ideas after we
all have read up on all these suggestions.  
Let the Multi-core Coco be born!
Kip

-----Original Message-----
From: coco-bounces at maltedmedia.com [mailto:coco-bounces at maltedmedia.com] On
Behalf Of Mark McDougall
Sent: Tuesday, April 30, 2013 8:48 AM
To: CoCoList for Color Computer Enthusiasts
Subject: Re: [Coco] FW: Multi-Processor 6809 Computer System

On 30/04/2013 6:09 AM, John Kent wrote:

> You can instantiate as many 6809 cores in an FPGA as it will fit in 
> the FPGA, although you will probably need block RAM cache as you would 
> need to share common memory between the CPUs. I was working on a quad 
> core 6809 system at one stage, many years ago, using a XC3S1000 on the 
> spartan 3 starter FPGA board from Digilent, but I ran into some 
> difficulties trying to work out the bus arbitration for shred memory and
never completed it.

FPGA's are perfect for prototyping this sort of design; you can design and
test many different solutions for no cost but your own time!

I haven't done a multi-processor design (other than cloning a few simple
arcade games) but we did do one design with two PCI interfaces that had to
share peripherals on a Wishbone bus. There is actually a white paper that
describes how to to bus arbitration on Wishbone, and we used that as the
basis of our solution (I seem to recall it was a purely combinatorial design
too). Of course there are several schemes and no doubt John's scheme as
described was just as valid.

Thinking purely off the top of my head - and this is less to do with
arbitration and more to do with inter-CPU I/O - in an FPGA design I'd
perhaps consider using blocks of dual-port RAM between each of the CPU's and
a designated 'master' CPU, with interrupts linked to mailbox registers. I
guess the master would be responsible for assigning tasks to each of the
slaves, and there'd be no (need for) slaves to communicate directly with one
another.

Hope you all have fun with it guys!

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"

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