[Coco] 6309/6809 opcodes with mixed 8/16 bit registers

[Luis Fernández]

I'm doing my utility CocoDSkUtil disassembler, and found that the documentation I have is inaccurate and sometimes erroneous.

--------------------http://www.lomont.org/Software/Misc/CoCo/Lomont_6809.pdf -----------------------------------
              A SECRET MEMO ON THE FEATURES OF 6309

       by Hirotsugu Kakugawa (kakugawa at csl.hiroshima-u.ac.jp)       Computer Systems Lab, Information Engineering Course,       Graduate School of Engineering, Hiroshima University, Japan
 --------------------------------   HD63B09EP Technical Reference Guide                                   By Chet SimpsonAdditions by Alan DeKok -------------------------------------
Errors in the 3













--------------------------------------------------------------------------------- 
Making  CoCoDskUtilPack V 1.1.3A.zip, Scan magazines and organize maltedmedia
http://cococoding.com/cocodskutil/ Thank Aaron Wolfe
http://www.tandycoco.com Thank Brian Blake and Stephen Fischer
My personal blog: http://www.luis45ccs.blogspot.com, 
Excuse my English, I use google translator, my language is Spanish, I'm Spanish but I live in Venezuela
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> Date: Tue, 20 Nov 2012 09:49:36 -0700
> From: hhos at st-tel.net
> To: coco at maltedmedia.com
> Subject: Re: [Coco] 6309/6809 opcodes with mixed 8/16 bit registers
> 
> > On Tue, Nov 20, 2012 at 2:14 PM, Harry Hurst <hhos at st-tel.net> wrote:
> >>
> >> One thing I've found, that may not be in your book, Darren, is that the
> >> supposedly "not allowed" modes [,R+] and [,-R] are actually functional
> >> on the 68B09E.
> >
> > Whoa, so do these increment and decrement the index register (to use
> > the next pointer next time) or the memory pointer? Hummm, since it's a
> > one byte increment it must be an increment to the memory pointer, it
> > wouldn't be useful otherwise. Am I right?
> >
> > But the question is valid for [,W++].
> >
> > I'm having some 6502 feelings here. Such feelings are never good.
> >
> >> They are "not allowed" in every reference I could find, and yet they
> >> work. I think most, if not all, assemblers disallow them, for good
> >> reason, but if the CPU encounters an instance of this, it will execute
> >> it just fine. The 6309 uses the [,R+] opcodes for some limited indexing
> >> with the W register. Here's a short list of these and other
> >> invalid-on-the-6809 indexing mode differences:
> >>                                 CPU
> >> Postbyte              6809               6309
> >> $90                  [,X+]("NA")           [,W]
> >> $B0                  [,Y+]("NA")           [n16,W]
> >> $D0                  [,U+]("NA")           [,W++]
> >> $F0                  [,S+]("NA")           [,--W]
> >> $87                   A,X (dup/$86)         E,X
> >> $A7                   A,Y (dup/$A6)         E,Y
> >> $C7                   A,U (dup/$C6)         E,U
> >> $E7                   A,S (dup/$E6)         E,S
> >> $97                  [A,X] (dup/$96)       [E,X]
> >> Presumably $B7, $D7, and $F7 follow suit for the Y, U, and S registers
> >> and are duplicates of $B6, $D6, and $F6.
> >
> Let's say the X register contains $EC00, the PC is at $EB00, and memory
> word at $EC00 is $8000. The instruction at $EB00 is $33 $90 which would
> mean LEAU [,X+] to the 6809. After executing this instruction:
> 
> PC: $EB02
> X:  $EC01
> U:  $8000
> 
> This is not useful. LEAU [,X++], on the other hand, which is a valid
> index/indirect form, can be quite useful. I just want to make my 6x09
> simulator as accurate as I possibly can, so I'm investigating as many
> non-valid, unlikely byte sequences as I can imagine. These are just a few
> that I have tested so far.
> 
> HH
> 
> 
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