[Coco] Are MC68B09E's and HM63C09E's as well as various support chips still available?

[John Kent]

Hi Kip,

VHDL or verilog (as Gary Becker uses) is not all that different from 
conventional programming languages in many ways. Rather than being 
restricted to 8 bit, 16 bit or 32 bit characters or integers, you can 
specify the exact length of the variables or registers in terms of bits. 
Rather than being held in memory the registers are implemented in Flip 
Flops. i.e. they are implemented in discrete logic, and as such they can 
be loaded in parallel with other logic. A case/when statement is similar 
to a switch/case statement in C but you generate hardware such as a 
decoder chip in the simplest case, or a multiplexer on a register input.

Most of the work in my FPGA 6809 is in the state machine sequencer that 
controls the instruction cycle sequence. The instruction cycles executed 
will depend on the decoding of the instruction opcodes and post bytes. 
It does not require much in the way of complicated maths, just control 
of the data paths between the registers and memory. Once you understand 
the underlying principles it's more a matter of tedium working through 
it all. Most of the operations say for calculating indexing modes, are 
just simple additions of the registers.

I was wanting to keep the operation of the CPU as fast as possible, 
however some software relies on the specific instruction cycle time to 
operate correctly. It might be generating an audio tone using a software 
timing loop. Other software might have a software timing loop to measure 
the horizontal sync position or active display period so the software 
can refresh the display during the synch and retrace time windows.

I can output the address and data bus of the CPU to I/O pins. It is 
possible to implement a programmable wait state generator for a specific 
window in memory. I could even design programmable address decoding like 
is done in the 68HC11. The issue was more with the old Motorola 8 bit 
peripherals that needed a 1 or 2MHz E clock, in which case you have to 
maintain a symmetric duty cycle of the clock, and you have to 
synchronize the CPU to that slow E clock to access the peripherals 
correctly. i.e. you have to wait for the start of the cycle to perform 
the access, then insert wait states in the CPU to perform the access 
during say the high E clock, then release it and continue on at the full 
speed.  It's not impossible to do ... it just requires a bit of work to 
work out how to do it cleanly.

OK on using the PDP-8e. I do actually have an FPGA PDP-8 design that 
uses a computer display and numeric keypad section of a PS/2 keyboard 
for the console. It also has a serial port I think, so you could 
possibly hook it up to an ASR33 teleprinter. I remember using an ASR33 
teleprinter back in my undergraduate days at university when I first 
learned programming on a Cyber 72.  The FPGA PDP-8 could run Focal out 
of memory as I recall. I haven't played with it in quite a while. It was 
originally written for a Spartan 2 FPGA board which Xilinx no longer 
supports. I did port it to a XESS XSA-3S1000 FPGA board, and it could 
probably be ported to other board too without much difficulty.

John.

On 27/05/2012 11:58 AM, Computer Doc wrote:
> John, Your skills and talents are quite impressive! I really like what 
> you are saying about coding the 6309 instruction set. Implementing a 
> microprocessor instruction set is very fascinating to me. I wish I 
> knew how to learn it all, but since I don't know beans about FPGAs and 
> VHDL coding or simulating 8-bit microprocessors - yet, I was wondering 
> is it important to add idle cycles to slow down the implementation of 
> the 6809 mode and why make the cycle timing accurate when you can make 
> it better and faster? I'm not criticizing, just curious. Since the 
> more recent technology runs so much faster, I've been trying to figure 
> out how to get a faster CPU with the 6809 and 6309 instruction set so 
> I can utilize the faster memories, serial port chips, etc. I'd like to 
> somehow wire up a 25MHZ COCO3 with added features in hardware as 
> opposed to software as many of you have done all in one FPGA which is 
> really cool by the way. It's all as fascinating now as it was in the 
> beginning learning computers in the first place 35 years ago. My first 
> experience was programming in BASIC in high school on an ASR-33 
> Teletype with paper tape reader and punch communicating over a 300 
> baud acoustically coupled modem over a phone line to Clemson 
> University's PDP-8e Minicomputer! Those were the days when you could 
> watch your program print out letter-by-letter. Whew, that took a 
> loooong time! (intentionally misspelled) I thought I'd share a little 
> of my very beginnings in high school. Thank you for taking time out of 
> your busy schedule to share your computer engineering prowess. I love 
> all your posts. They are always informative. It's a real treat to be 
> able to communicate directly with people whose articles I've read over 
> the years and appreciated. Kip
http://www.johnkent.com.au
http://members.optusnet.com.au/jekent