[Coco] 65k colours serial VGA module

[John Kent]

On 22/05/2012 10:17 AM, Mark McDougall wrote:
> On 22/05/2012 1:05 AM, John Kent wrote:
>
>> If you can double the pixel clock and line rate you may be able to 
>> drive a
>> VGA display with the CoCo output. i.e. the FPGA graphics controller 
>> would
>> double as a scan rate converter.
>
> In Altera PLLs you can specify the phase offsets so I'm sure this 
> would be doable.
>
> Regards,
>

Hi Mark,

Yes, I know T. Franklin and a number of others are using the DE1 board.

What I was thinking was that based on discussions on this list, I 
thought a lot of members had bus expansion boxes on their CoCos that 
allowed them to plug in expansion cartridges, and I assume PCBs also. I 
thought that if they were using that scheme, then there was probably a 
prototyping card that people could put their own logic on.

The DE1 board is fine but it costs about US$240 whereas the XuLA board 
is only about US$80 or so, so it's 1/3 the cost. It doesn't do nearly as 
much as the DE1 board, but it's much cheaper. It would be possible to 
add an interface board for the DE1 board to the expansion box. You'd 
need 5V to 3.3V level translation to interface to the FPGA board. You'd 
also want a 40 pin IDC connector mounted on the CoCo expansion board 
that was pin compatible with DE1 board so you could use a standard IDE 
hard disk cable to connect the two.

The PLL (Phase Locked Loop) block in the Altera is similar in many ways 
to the DCM (Digital Clock Manager) in the Xilinx FPGAs. There was a 
concern expressed some time back that some people didn't want to be 
getting into their CoCos and soldering wires onto the 14MHz (?) crystal 
oscillator inside the CoCo used to generate the pixel clock. I'm 
assuming the Coco divides down the pixel clock to generate the CPU clock 
so that the two operate synchronously so they can multiplex the memory 
bus. I'd have to check the circuit again to see what is done.

I'm assuming the CPU E clock of 791KHz or what ever it is, is available 
on the expansion port. If you wanted say a 28MHz pixel clock to generate 
VGA timing, then you'd need to divide the FPGA clock by 32 or more, to 
lock the divided signal to the CPU clock. Since the PLLs and DCMs are 
self contained in the FPGA, they will need to have that division ration 
available in their design. They do have clock doubling functions, in the 
Xilinx DCMs at any rate and probably in the Altera PLLs as well so it's 
easy to multiply up the pixel clock, but if you have to lock it onto the 
CPU clock then that's probably a bit trickier. I thought the Xilinx DCMs 
also had multiply and divide ratios, but whether that extends to ratios 
as big as 32 I'm not sure. Also a large divide (multiplier) ratio may 
also introduce noise and jitter into the pixel clock. There is no loop 
filter in the FPGAs to filter the noise out.

The alternative would be to build an external PLL circuit to generate a 
clock for the FPGA. There might be PLL chips out there designed to do 
that but It makes the design more complicated.

That was my thinking anyway.

John.

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