[Coco] A Technical Question

[Steve Bjork]

On 5/17/2012 9:02 AM, T. Franklin wrote:
> I have atechnical question about the video link and RAM on a computer (not necessarilya CoCo). I'm creating my own 6809 basedcomputer on an FPGA and stuck on a direction as to implementation. It has to dowith the write CPU cycle of the video area. Is it normal to allow the CPU towrite to video RAM only during the refresh&  blanking? If so, is it normalto use a dual port RAM scheme or is the processor held in a wait state until thehorizontal scan is complete?
While Sega and Nintendo games systems of the time of the CoCo could only 
write to Video Ram during the V & H blank, the CoCo did not have this 
limitation.

The CoCo's memory was shared equality between between the CPU and the 
Video system.  One RAM cycle is feed to the CPU and the next cycle is 
read for the Video.  Basically,  memory is synch-lock between the two 
systems.  This why the CPU speed is based on the video timing.  The 
Dynamic RAM refresh is done during the unused part of the Video RAM access.

Knowing how the CoCo works on the basic hardware level is key to the 
project you are trying to undertake.  I would do a lot more study before 
taking on a project like this this.

> Some of theideas I had with this venture is to (like others) implement a CoCoin an FPGA but modify all the graphics routines (i.e. lines, circles, draws andPCLS) to all FPGA core implementation. I?m thinking about adding a 3D FPGA coreimplementation similar to OpenGL for some real cool CoCogaming.
Yes, you could FPGA blitter to draw some graphics.  But OpenGL 3D 
graphics?  What about the 3D matrix translation and Object texture maps 
used in OpenGL?  How are you going to build anything like that in 
today's FPGA kits?
> This is just mydream but as I slowly get started, I?m finding that questions like this oneplague me for weeks. So any help would be appreciated.
>
> See you all atCoCoFest!!!
>
>