[Coco] New thread, cga-rgb->vga convertor GBS-8220

[Mark McDougall]

On 29/07/2011 1:31 AM, Mark Marlette wrote:

> All
> of our designs are in SVN so when I pull the design up with a new version
> of Quartus, the local repository is modified but I do not commit the
> converted database.

Schematics aside, you need only retain the .qpf, .qsf, source files and any 
extra timing/script files (.sdc, .qip, etc) in revision control. No need at 
all (and a serious waste of space) to retain the 'db' directories, or all 
the other reports and such created in the project directory.

The really nice thing is that - unlike Xilinx tools - With a pure HDL 
(VHDL/Verilog) design, you only ever require *text* files in SVN.

And as you know your .SOF/.POF/.RBF/.JIC bitstream files are all you 
ultimately need to run your design.

> This was done in a
> hierarchical schematic design, currently three levels deep. I am just
> starting to learn .vhdl. Big difference in editing and creating. :)

Went down the same path as you. When you finally switch all your designs to 
HDL your life will be *much* *much* easier! As will revision control! ;)

> I haven't tried it yet but it appears that I can make .v code from my
> schematic design and transfer that file to the new designs.

IIRC you can create VHDL or Verilog from a schematic. It's a little verbose 
and the naming convention obtuse, but it's a great place to start!

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"