[Coco] 6x09 read and write strobes.

[john dumas]

On 12/19/2011 5:14 PM, jdaggett at gate.net wrote:
> On 19 Dec 2011 at 8:48, john dumas wrote:
>
>> The 6809 die plots that I saw did not have a PLA for the decode logic,
>> but used random logic gates.
>> IIRC Bryant and Dennis busted their buns cramming in the logic,
>> maintaining that array logic
>> like PLAs would eat up too much die area. As an aside, the push to keep
>> the smallest die
>> size was the central element of a continuing - friendly - battle between
>> Terry and Joel on
>> one side and Bryant and Dennis on the other. ....A common tension
>> between "features"
>> and "producibility" in those days..........
>> Been there, done that.... on both sides myself!
>>
>> In the end , the 09 ended up like the 00, with random logic. Later
>> designs went to array logic,
>> microcoded, etc...
>>
>> cheers,
>> johnd
> PLA may not be exactly the best way to describe the input circuitry.
Nope.
>
> > From the 6800 patents and the schematic in there, the instruction opcode goes to a register
> and then there are 16 lines which are each bit and its associated inverted level. Those
> sixteen lines feed the random logic and the equations for each instruction execution. In a
> rudimentary form it is a PLA. Though not like a common PLA which are ands and ors to
> make up the product terms.
Have to disagree there. As I remember the 00 and '09 instruction decode, 
it was
nothing like a PLA - or any form of array logic. The IR did of course 
feed true and
false forms of each bit to the decode, but the physical form (layout) of 
the decode
was purely random logic gates. (Sure wish I still had a die photo to 
'fresh my tired
memory cells! Wife says that when I retired, I left my brain at the 
office. D'oh))

In that time and place, a PLA was a regular (array) structure with the 
logic being
implemented purely with the gate level mask set.  Cut a thin-oxide area 
between
parallel diffusion runs (the array) and you "placed a xistor". The logic 
could be
changed without changing any mask other than the gate level.
Penalty? Always max size........ Sometimes one could use a "half-PLA" - 
the AND
section - only, but it still was bigger than random logic if you had a 
really talented
draftsperson to lay out the random logic and enough slop in your schedule to
allow "tweaking" the layout........

Loved using PLAs when I worked at TI and Bowmar. Die size wasn't as 
critical with
the management, but schedule sure was, and a PLA implementation was fast.
And, of course, it was much easier to correct my many boo-boos!!! (grin)

cheers,
johnd


>
> The way I understand the Instruction Modiication Register patent, the Page1 and Page 2
> opcodes modify the lines that feed random logic for instruction execution.
>
> james
>
>
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