[Coco] 6x09 read and write strobes.

[John Kent]

Hi James,

Yes, I just wasn't sure what the phase relationship was with the Q 
clock. Looking up the data sheet for the 6809, the falling edge of the E 
clock is followed by the rising edge of the Q clock, so my timing 
diagram was correct.

The address bus and read write lines should be set up in time for the 
rising Q clock. It was stated that both Q & E clock lines where used in 
conjunction with the read write line to generate read and write strobes. 
You could do that to lengthen the access time of the peripheral but 
write data from the CPU is normally set up just before the E clock goes 
high so there is little to be gained by lengthening the write strobe.

WR = (E or Q) and not(R_Wn)

When reading peripheral data into the 6809 data needs to be set up 
80nsec before the falling E clock edge for a 1MHz part which is actually 
after the falling edge of the Q clock. In that case:

RD = E and R_Wn

But it depends on how long RD and WR need to be set up before there is 
valid data on the bus.

In my FPGA 6809 design I use the falling edge of the CPU clock, to clock 
the values into the registers, and to transition the state sequencer 
that determines the sequence of CPU instruction bus cycles.

My FPGA 6809 uses a single phase clock. It is necessary that the CPU set 
up the address bus and the data bus on write before the rising edge of E 
so that I can use the synchronous RAM in the FPGA. The synchronous RAM 
clocks the address and data input on a rising clock edge.

The 6809 was NMOS. I'm not familiar enough with the NMOS technology to 
know how the internal clock phases worked. The 6800 had the requirement 
that phase 1 and phase 2 of the input E clock not over lap and they had 
special clock chips, the 6871 and 6875 (?) to do it.

John.

On 19/12/2011 1:05 PM, jdaggett at gate.net wrote:
> John
>
> The circuit that I described is off the SIMON6809 board. It is used to access external RAM
> and EEPROM. The ram is a 32K  and the EEProm is a 2865 8K part.
>
> The MC6800, 6801,6802, 6805, 6809 and 6811 all use the faling edge of the E-Clock to start
> the machine cycle. All hae internal clocks that are out of phase from the E-clock. It is a bit
> confusing to state which clock leads whom. It is all a matter of where you call the starting
> point for a machine cycle. For the 6809 the Q-Clock is used for internal along with, I believe,
> an inverted E-clock if Iread the schematic of the 6800 correctly. The 6809 used the same
> basic archetecture as the 6800. They reprogrammed the internal PLA for different
> instructions and added some other circuits. One was an Intruction Set Modify Register for
> which there is a patent for that. The opcodes $10 and $11 affectionately called pre-bytes
> actually modify the opcode following by changing the output of the PLA in the intruction set
> decode logic. The other main circuit added was the Fast Interupt Circuit. Again a patent was
> awarded for that. That gave the 6809 the FIRQ, a second interrupt source.
>
> The Motorola processors used the rising edge of the E-Clock to tell the peripherals that it was
> using the bus. In the COCO that is why the video acceses ram while the E-clock is low.
> Peripherals can then be interleaved with the CPU clock cycles. The positive E-clock acts as
> an enable. This is opposite polarity of the Intel system.
>
> james
>
>

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