[Coco] What would a CoCo successor have to have as a minimum?

[jdaggett at gate.net]

On 21 Nov 2010 at 19:27, Theodore (Alex) Evans wrote:

> As far as the bandwidth issue goes, assuming that we are talking about a 
> 25MHz CPU, there are SRAMS that are at least 12x as fast as the CPU, so 
> interleaved data access lets the "blitter" consume a lot of bandwidth 
> without interfering with the CPU assuming you latch the data for the CPU 
> somewhere.  Since the CoCo 3 already supported hardware scrolling, you 
> shouldn't need to blit a full screen just because you are scrolling in 
> one direction or another.  Remember that most old CoCo games did not 
> redraw the entire screen on a regular basis.  With all the talk about 
> the Amiga, the Amiga did not generally blit the entire screen when 
> scrolling, and it reduced the memory bandwidth problem by separating 
> chip and fast memory.
> 
> 


With a 25MHz bus rate 6809, the fastest SRAMs are only 5x fster. The fastest SRAM that I 
can find on the market is 8nS access time. I have 1Megx16 8 nS SRAMs now for a COCO3+ 
project. ISS61WV102416BLL are rated 8nS access at 3.3 VDC. 10 nS at 2.5VDC. 

If you are going to do interleaved DMA like the COCO3, then the ram has to be twice as fast 
as the bus rate. So with 25 MHz CPU bus rate you will need 50 MHz SRAM minimum. 

SDRAM can operate at 3.5nS. Throw in DDR and its successors and you have even faster 
parts but they are dynamic chip and not static chips.  SDRAM pose issues that are not there 
with SRAM. 

james