[Coco] What would a CoCo successor have to have as a minimum?

[Mark McDougall]

On 21/11/2010 2:49 PM, John Kent wrote:

> I might also add that the software emulator has to perform memory decoding,
> bounds checking and memory mapping all sequentially. It also has to emulate
> the hardware, which is presumably on an an I/O space access, but may also be
> concurrent with the CPU execution. The FPGA does this all in parallel. So
> even if there are say 100 CPU cycles to one FPGA clock cycle there is a lot
> the CPU has to do in those 100 cycles.

You're right of course John, but you also have to take into consideration 
the efficiency of modern CPU design, with pipelining, hyper-threading etc. 
Most of the effort emulating a Coco is churning the CPU emulation. Unlike a 
real Coco - or even FPGA - half the emulated memory is probably cached in 
the processor too.

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"