[Coco] Interesting reading

[jdaggett at gate.net]

Lothan

SWI/SWI2/SWI3 are opcodes and these interrupts are processed after the opcode fetch and 
before execution. The HALT/NMI/FIRQ/IRQ inputs are processed prior to opcode fetch. 
There is logic to prevent simultaineous IRQs. If the NMI and IRQ arive at the same time, the 
NMI priority circuit should prevent an IRQ fro happening. The IRQ will never get latched. Or 
at least that what it looks like in teh circuit description. Also an interesting thing I read. There 
is a hidden opcode in the microcontrol. FWA( Forward and Wait). This is issued when a 
CWAI instruction is encountered and a maskable interrupt occurs before the CWAI opcode 
can put the processor in wait for interrupt state. The FWA prevents the microcontrol from 
executing an opcode fetch from ROM. 

I really looks as they thought through the process for many events and issues that could 
happen.

james

On 20 Jun 2010 at 0:03, Lothan wrote:

> From: <jdaggett at gate.net>
> 
> > A while back I was doing some patent searches and came across several 
> > Motorola Patents
> > on the 6800 series processors. I also came across two other patents that 
> > covered the FIRQ
> > function.
> >
> > Well today I really started in depth reading of one patent. Well needless 
> > to say it is been very
> > educational. Figure #7 of the design and the corresponding description of 
> > it is enlightening on
> > how the hardware inputs work. From everything I read the embodiement 
> > processor for the
> > invention is the MC6809. No other processor of that time had Reset, Halt, 
> > NMI, FIRQ and
> > IRQ external hardware inputs. Patent US-4200912, Processor Interrupt 
> > System, describes
> > much of the logic behind the MC6809 interrupt system and how it works.
> >
> > I have gathered this from the patent. There is a priority assigned to the 
> > external inputs. They
> > are as follows:
> >
> > RESET   1 (highest)
> > HALT    2
> > NMI    3
> > FIRQ      4
> > IRQ        5  (lowest)
> >
> > Also the priority circuit allows for an asychronous reset to occur and if 
> > in HALT mode, once
> > the HALT input is released a RESET occurs.
> 
> This is really interesting. I didn't realize there was priority logic in the 
> interrupt handling logic. The "MC6809-MC6809E 8-Bit Microprocessor 
> Programming Manual" published by Motorola gives somewhat the same priority 
> levels but seems to base the priority on how the interrupts are latched, 
> whether the interrupts can be masked, which interrupts are automatically 
> masked, and so on. I had just assumed that was the case, so this is very 
> enlightening.
> 
> The priority given given in the first paragraph of Section 3 is NMI, SWI, 
> FIRQ, IRQ, SWI, SWI2. What I don't know is whether SWI actually has a higher 
> priority (e.g. will the 6809 process an SWI interrupt even though it 
> received an FIRQ or IRQ at virtually the same time) or if it's just saying 
> SWI is considered a higher priority in a virtual sense because it sets and I 
> and F bits (masking IRQ and FIRQ) before jumping to the SWI vector. I 
> suspect it's the latter, but I'm curious if anyone knows the details here.
>  
> 
> 
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