[Coco] Interesting reading

[Darren A]

On 6/19/10, Lothan wrote:
>
>
> What I don't know is whether SWI actually has a higher
> priority (e.g. will the 6809 process an SWI interrupt even though it
> received an FIRQ or IRQ at virtually the same time) or if it's just saying
> SWI is considered a higher priority in a virtual sense because it sets and I
> and F bits (masking IRQ and FIRQ) before jumping to the SWI vector. I
> suspect it's the latter, but I'm curious if anyone knows the details here.
>

--

I agree that is probably the latter.  The reponse to an IRQ or FIRQ
cannot occur until after the current instruction has completed.  If
the current instruction were an SWI, its completion would include
setting the I and F masks. This would prevent the CPU from responding
to the IRQ or FIRQ before the SWI.

Darren