[Coco] How does the SCS line / GIME Setting Work?

[jdaggett at gate.net]

The MC2 bit of the INIT0 ($FF90) register controls what is encoded onto the S BUSS when 
the MPU addresses in the range of $FF40 to $FF5F. Only a 16 bit window is active at 
anytime. When the MC2 bit is set then we have the standard SCS which is encoded as $011 
on the S BUS and then when the MPU addresses in the range of $FF40 to $FF4F then bit #6 
of the LS138 is asserted low. When the MPU accesses adress rang $FF50 to $FF5F then 
the SBUS will have $001 encoded on it and bit #4 of the LS138 is asserted low. Bt #4 never 
goes to the expansion connector. Thus leavign the implication that an internal drive controller 
was a potential upgrade. 

If the MC2 bit is cleared the opposite of the above is true. The SCS line to the expansion 
connector is asserted when the MPU addresses $FF50 to $FF5F and not $FF$0 to $FF4F.


I hope this is clear????

james

On 19 Jun 2010 at 7:06, Darren A wrote:

> 
> You are correct.  The SCS line is an Address Decode signal that
> 'normally' indicates an address access from FF40 to FF5F.  This
> originated from a feature of the SAM chip which outputs a unique
> address code for the ranges FF00-FF1F, FF20-FF3F and FF40-FF5F (among
> others).  The first two were used internally for selection of the
> PIAs. The third was considred a spare and thus given the name "Spare
> Chip Select".
> 
> The GIME's SCS bit in FF90 will restrict the SCS range to FF50-FF5F
> when off.  Softawre which communicates with the FDC does so through
> addresses in the FF40-FF4F range, so turning off this bit will
> effectively disable the disk controller.
> 
> Darren