[Coco] How does the SCS line / GIME Setting Work?

[jdaggett at gate.net]

Brett

The SCS function of the GIME is asserted only when the address is between $FF40 and 
$FF4F when the MC2 bit in the INIT0 register is set. Otherwise it is active between $FF50 
and $FF5F when the MC2 bit is cleared.  This signal is encoded into the S-bss out of the 
GIME chip.

Not totally sure why this was done. Many believe that the next progression would have 
possibly added an internal drive to the COCO. With some rework an internal drive using one 
of the 2.5/3.5 inch IDE drives is possible. In any event with some work this can allow both an 
internal and extrernal drive either hard or floppy.

james

On 19 Jun 2010 at 7:37, Brett Gordon wrote:

> I hope this isn't too silly of a question to ask.  I'm foggy on the workings
> of the SCS line and how the SCS setting on the GIME chip effects it.
> 
> >From what I gathered the SCS line is asserted when the address bus is from
> 0xFF40 and 0xFF5F.   I assuming it's a specialized address line used to
> "help" the FDC out. I'm assuming a FDC pack could do this itself if it
> wanted too.  I'm figuring Tandy wanted to make their FDC a bit cheaper, so
> added this line to the CoCo's Cart port.  Is there any other *regular* uses
> for this line?
> 
> And exactly what does the GIME's SCS enable do in 0xFF90 ?  I seem to
> remember playing with this setting once, and my FCD software stopped
> working.  So if your GIME's SCS's bit in 0XFF90 is off, the SCS will never
> be asserted?
> 
> Pardon my ignorance....
> 
> -- 
> Brett M. Gordon,
> beretta42 at gmail.com
> 
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