[Coco] hardware question - coco3 RAM subsystem

[jdaggett at gate.net]

On 26 Mar 2009 at 19:22, Stephen Adolph wrote:

> As I stare at the schematic the functionality is becoming more clear.
> 
> One question-
> The CPU cannot complete it's read in a single pulse of the E clock -
> so that data has to be available on the correct edge in the next phase
> (from the 6809 data sheet).
> 

Yes it does. The ram is accessed at twice the fastest speed of the CPU. At 
fast speed the CPU machine cycle is 579nS. The ram read cycle is 260nS. 

> Does the GIME store the data for the CPU, obtained in the SAME E CLOCK
> pulse as the CPU request, and forward it to the CPU during the next
> phase?  ( I suspect the answer is yes..)
> 

Nope. It is passed through a multiplexor out the CPU databuss. The read 
data is clocked inon the falling edge of tehE-Clock on a read cycle. The 
GIME need only hold the data on the buss for 20nS after the fall of the e-
Clock.

> So, from the RAM's perspective, each read/write, regardless of source,
> completes within a single pulse of either E or Q?
> 

The GIME reads the ram twice as fast as the CPU. It will do two reads for 
every machine cycle at fast speed. The GIME is designed to work with 
150nS access DRAM. That speed DRAM has a read/write cycle time of 
260nS.

james


> thanks.......
> 
> And yes, my RAM is 16 bits wide - 2 words independantly organized,
> thank goodness.  Clearly needed.  (although, I think fast 8 bit ram
> could also work with enough buffers).
> 
> 
> 
> 
> On Thu, Mar 26, 2009 at 7:03 PM,  <jdaggett at gate.net> wrote:
> > Stephan
> >
> > First off the COCO3 DRAM is configured in 256Kx16 mode using 41256
> > drams.  DRAM access is fixed time and is accessed via a method known
> > as IDMA(Interleaved DMA). That is when the E Clock is low the GIME
> > accesses the memory for video. During the protion when the E Clock
> > is high the CPU will write to memory. All reads of memory pass
> > through the GIME chip.
> >
> > If your SRAM can be used in either 8 or 16 bit data buss mode then
> > with fast enough external glue logic it maybe possible to be used in
> > a COCO3.
> >
> > james
> >
> > On 26 Mar 2009 at 11:13, Stephen Adolph wrote:
> >
> >> Hi folks,
> >> new to list, nice to meet you all.
> >>
> >> Ok, here is my question.  Looking at the 512k upgrades for Coco3, I
> >> understand this is a DRAM based system.
> >>
> >> I happen to have a large amount of 2MB SRAMs, and a custom board
> >> with a CPLD, that could be used to do a variety of things.
> >>
> >> (actually it is a ReMem for the M100 - see www.istop.com/~sadolph -
> >> that's me.) (I want to reuse some existing memory hardware to
> >> upgrade the COCO3 I have).
> >>
> >>
> >> So, I am looking at the 41256 data sheet, and thinking about using
> >> SRAM instead of DRAM.
> >>
> >> But, 41256 has some memory modes "page mode" that allows the row to
> >> remain while the column is stobed..to up the read/write rate I
> >> presume.
> >>
> >> Does COCO3 use these modes? OR, does it always operate in such a
> >> way that CPU bus memory address always translates to one and only
> >> one memory read/write?
> >>
> >> OR, could I simply capture ROW and COLUMN and create my own address
> >> from that.
> >>
> >> ( I don't know enough about how the GIME chip manages the ram is
> >> what this boils down to.)
> >>
> >> pls advise if possible.
> >>
> >> cheers,
> >> Steve
> >>
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> >
> >
> >
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