[Coco] hardware question - coco3 RAM subsystem

[Mike Pepe]

Hey Steve,

Sounds like an interesting project, and I know of at least one other
person on this list who has successfully demuxed the DRAM address bus
and used srams to upgrade a CoCo3

The CoCo does not address the memory in any way other than a standard
RAS/CAS cycle.

The CPLD is probably serious overkill for what you need to do. A couple
of LS latches would do the trick for less than a buck.

All you really need to do is use a couple of latches to grab the row and
column addresses and turn them back into a linear address you can feed
into an array of SRAMS.

When you say 2MB I assume you mean 2 megabit meaning they're probably
256k x 8 in size? I think that would work out well as you need to make a
16 bit wide array to most easily feed the GIME.

If all you want is to upgrade a CoCo3 to 512k and you think your time is
worth more than 40 bucks, go here

http://www.cloud9tech.com/

and click on the hardware tab for the upgrade board. I've bought
probably 4 of them and they work great.


-----Original Message-----
From: coco-bounces at maltedmedia.com [mailto:coco-bounces at maltedmedia.com]
On Behalf Of Stephen Adolph
Sent: Thursday, March 26, 2009 8:13 AM
To: coco at maltedmedia.com
Subject: [Coco] hardware question - coco3 RAM subsystem

Hi folks,
new to list, nice to meet you all.

Ok, here is my question.  Looking at the 512k upgrades for Coco3, I
understand this is a DRAM based system.

I happen to have a large amount of 2MB SRAMs, and a custom board with
a CPLD, that could be used to do a variety of things.

(actually it is a ReMem for the M100 - see www.istop.com/~sadolph -
that's me.)
(I want to reuse some existing memory hardware to upgrade the COCO3 I
have).


So, I am looking at the 41256 data sheet, and thinking about using
SRAM instead of DRAM.

But, 41256 has some memory modes "page mode" that allows the row to
remain while the column is stobed..to up the read/write rate I
presume.

Does COCO3 use these modes? OR, does it always operate in such a way
that CPU bus memory address always translates to one and only one
memory read/write?

OR, could I simply capture ROW and COLUMN and create my own address from
that.

( I don't know enough about how the GIME chip manages the ram is what
this boils down to.)

pls advise if possible.

cheers,
Steve

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