[Coco] MCM68766

[jdaggett at gate.net]

On 14 Jul 2008 at 9:23, Chuck Youse wrote:

> On Sun, 2008-07-13 at 23:21 -0400, jdaggett at gate.net wrote:
> > Mike
> > 
> > You need 250nS access time for the ROM memory for the Coco to run at
> > 1.78MHz period. On the ROMs and static ram the access time and the
> > cycle time are equivalent. The maximum access time is the fastest
> > that the ROM can operate at. The inverse of 350nS is about 2.85MHz.
> > Since the Coco uses IDMA to access both data and video memory, at
> > 1.78MHz half of the 560 nS cycle time is used to access data/program
> > memory. The other half is used to access video memory.  That is
> > 260nS for a read cycle at 1.78MHz. This means in a Coco system the
> > fastest clock for 350nS ROMs is about 1.425 MHz. Like I said before
> > they work fine with the clock at 0.89MHz 
> 
> I think that you're perhaps over-complicating the situation; the
> access-interleaving done by the GIME really only applies to the
> dynamic RAMs -- the GIME does not get in the middle of bus cycles for
> ROMs or I/O regions, except as an address-decoder (S[2:0]).
> 
> The access time of the I/O ports and EEPROMs must be < ~280ns, not
> because of any interleaving, but because an access begins on the
> positive edge of the E clock, and is completed on the negative edge
> (more or less).  At 50% duty cycle that means the access time is
> roughly 1/2 the period of the system clock.
> 
> Or did I miss something?

Access time of ROMS is equal to the read cycle time. Thus for an access time of 350nS that 
is speced from the time that the address is valid to the time that the data is outputed from 
the ROM. In the 6809 the address is valid approxiamtely on the falling edge of the Q Clock. 
Data is clocked into the processor on  the next falling edge of the E Clock. The 6809 cycle 
starts on the falling edge of the Eclock.


james