[Coco] *WTH!?* iniCPU: A modern 6809-compatible CPU !!

[Joel Ewy]

Fedor Steeman wrote:
>> I'm guessing you all realise that this is a soft core, to be targeted
>> to an FPGA/ASIC and that you can't buy the silicon?!?
>
> No, I didn't realize that. I genuinely thought they were manufacturing
> the
> chips themselves... :-(
>
> I wonder how costly it would be to turn these designs into a bunch ICs?
>
There are already free, Open Source 6809 opcode-compatible VHDL cores
available that can be implemented in FPGA.  Putting one of these in an
FPGA isn't terribly difficult or prohibitively expensive (I gather). 
The consensus seems to be that ASIC pretty much out of the hobbyist
realm.  This particular design might be better optimized (at the moment)
than the Open Source stuff that's available, though I don't see any
indication that that is necessarily true.

We've had quite a bit of discussion about CoCo 3 / (4/5) Systems On a
Chip (SOCs) in FPGA (with additional circuitry for I/O / analog
support).  But I don't see any reason why one couldn't in stead use an
FPGA board to implement just a high-speed 6809 processor and plug it
into a real CoCo.  The bottleneck of course would be the system bus,
which would still be limited to 2MHz.  And it wouldn't add any features
to the GIME, like better graphics or support for more RAM.  This would
be like a souped-up version of the 4MHz circuits by Sockmaster (and
others).  I/O would still be limited to 2MHz, but all internal
processing would take place at whatever speed the FPGA could be clocked
at.  I know that the System09 was clocked at around 12MHz in one
configuration.  Presumably, with the right FPGA you could go to 40M, or
maybe more.  I know that others on this list have mentioned that some of
the faster, more recent FPGAs are not 5V tolerant, and so couldn't be
used here (at least without some kind of intermediate circuit to bridge
the 3V-5V gap).  But even a 12MHz 6809 would be a significant
improvement for the CoCo.

How difficult would it be to implement a cache on the FPGA?  You could
have a whole 64K of data and instructions cached on-chip and only hit
the external bus when you need to do I/O.  Is there anything required on
a system bus level to maintain cache coherency that couldn't be done
internal to the FPGA? 

That would be a nice intermediate step along the road to a next gen
CoCo, and it would provide a viable upgrade to people's existing Color
Computer systems.  If somebody could come up with a kit for a CoCo
high-speed CPU replacement that would sell for <$200 that you could plug
in in place of the 6809, that might be able to help fund a more
ambitious CoCo replacement project.

JCE
> Cheers,
> Fedor
>
> On 27/02/07, Mark McDougall <msmcdoug at iinet.net.au> wrote:
>>
>> Gene Heskett wrote:
>>
>> > A more interesting question would be, can it be made 6309 instruction
>> set
>> > compatible?
>>
>> With the source, of course!
>>
>> I'm guessing you all realise that this is a soft core, to be targeted to
>> an
>> FPGA/ASIC and that you can't buy the silicon?!?
>>
>> Regards,
>>
>> -- 
>> |              Mark McDougall                | "Electrical Engineers
>> do it
>> |  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"
>>
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