[Coco] [Color Computer] Re: POKE 65495,0

[Phill Harvey-Smith]

jdaggett at gate.net wrote:
> On 4 Feb 2007 at 4:21, James Diffendaffer wrote:
> 
> DRAM chips are specified for a period of time in which  the memory cell needs to 
> be refreshed. The basic construction of a dynamic ram cell bit is a well something 
> like a capacitor that holds charge and a NMOS transistor that acts as a switch. 
> The well that stores charge has a leakage path through the p type material of the 
> IC substrate to gorund. That leaskage path in combinatin with the low value of 
> capacitance that storage well presents has a defined period in which charge is 
> bled off to a level that is in the undefined region of standard TTL range for logic 
> levels. Depnding on IC construction this period is between 4 milliseconds and 
> about 100 milliiseconds. 
> 
> By "good" I mean that  you have a set of ram chips that hold the well charge 
> longer than the specified time period. Still I have reservations that any dram can 
> retain a logic "one" charge for upwards to 8 seconds without refresh. 

Whilst I agree with all of the above description of the inner workings 
of the DRAM chip, and also what the data sheets say with respect to 
refresh, they still don't explain why one of my CoCo 2 machines, which 
has 2x4464 ram chips, can be turned *OFF* for several seconds and retain 
the ram contents.

This is actually quite a pain at times, as if the machine crashes in 
such a way as a soft reset can't recover it then I have to leave it off 
sometimes for up to 30 seconds.

Strangely my CoCo 2 with the daughter card with 8x4164s does not suffer 
from this.

>									Also I have 
> to point out that there is a remote possiblity that there is an error in the MC6883 
> data sheet. That is to say that switching to high speed may "not" disable the 
> refresh grants. That is the first t hing that comes to mind when  you report such 
> long periods of dram retention. 

Humm I have found that leaving it in fast mode for too long does lead to 
ram corruption, especially on machines using 4116/4164 DRAMs.

This should be easy to verify, make a rom cartage that disables 
interrupts, sets fast mode and then goes into an infinite loop, so that 
the CPU will never access the RAM, then you would need to look for 
activity on the CAS and RAS lines. Though I think the 6809 data sheet 
says that when the CPU does not use the external bus it effectively 
generates a read of $FFFF, this should not cause a DRAM read as this is 
mapped by the SAM to ROM, for the boot vectors.

Cheers.

Phill.

-- 
Phill Harvey-Smith, Programmer, Hardware hacker, and general eccentric !

"You can twist perceptions, but reality won't budge" -- Rush.