[Coco] [Color Computer] Re: POKE 65495,0

[James Diffendaffer]

James, if your read back through the tread you'll find we were talking
about running the CoCo 1/2 in SAM high speed mode with the RAM refresh
disabled.  

You can run a program faster this way but you have to enable the
refresh about every 4 to 4.5 seconds to keep DRAM from loosing it's
contents.
The alternative is to do a read on each column at least every 4
seconds.  By my calculations, one read each interrupt should let 64K
RAM hold it's contents just fine.  For 32K it could be every other
interrupt.

60 interrupts / sec for NTSC 
256 rows for 64K or 128 rows for 32K

That means it takes NTSC about 4.27 seconds to refresh 64K and half
that for 32K.  PAL might not be able to refresh a full 64K fast enough
since it takes over 5 seconds using 1 read / interrupt.


--- quoted message follows  ----------------------------------
On 3 Feb 2007 at 6:27, James Diffendaffer wrote:


> A version for the CoCo 1/2 would be easy enough. The Coco3 GIME

> doesn't work the same as the SAM so it probably doesn't need a similar

> program.

>

************

Both the SAM and the GIME chips have refresh counters and all the
necessary
intergratin to carry out refresh. There is no real need for any
ancillary program to
do refresh to the dram memory. In fact both should do primarily the same
function as the 4164's and the 41246's both require all 256 rows
refreshed within
4 mS. Also both the SAM and the GIME chip do IDMA. There are other methods
but IDMA works fine for slower CPU clock speeds of that generation of
processors. Even True DMA has some limitations as CPU clock speeds get
higher. SDRAM controllers are nice in that a multiport interface can
be built
around them such that the SDRAM controller now coordinates whom and when
reads and writes to the SDRAM.


james