[Coco] 6809 Test and Set instruction?

[William Astle]

Roger Merchberger wrote:
> Rumor has it that Allen Huffman may have mentioned these words:
>> Does the 6809 have a test and set instruction?
> 
> Assuming I understand your question, yes.
> 
> TST
> TSTA, opcode 4D
> TSTB,    "   5D
> 
> The memory TST instruction works with these addressing modes:
> 
> Direct:    opcode 0D
> Extended:    "   7D
> Indexed/Indirect: 6D

I believe he's referring to an "atomic test and then set" instruction 
which is often used in synchronization between simultaneous threads of 
execution. The idea is that the instruction tests a memory location and 
then sets it. Thus, the CC register would have the result of a TST 
instruction but the memory location would be, for example set to $FF 
afterward. Note that in this case the test-and-set instruction has to be 
atomic on the physical bus as well as inside the processor.

Unless one is doing multiprocessor systems, it shouldn't be an issue not 
to have one since the 6809 does not process pending interrupt requests 
until it finishes executing the current instruction so it would probably 
be possible to simulate the "test and set" wrt the NMI using some 
gimickry with INC or CLR or something. (You can just disable FIRQ or IRQ 
after all.)

-- 
William Astle
finger lost at l-w.ca for further information

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