[Coco] Re: [Color Computer] Re: Interfacing question.

[Phill Harvey-Smith]

j_e_daggett wrote:
> 
> Phil

Phill :)

> What pin of the 22V10 is the A3 line driving? Pin #1 is either an

Initially pin 9 later pin 13 (re-routed to try and make sure it wasn't 
some weird thing about pin 9).

> input or a clock input. It is advisable that pin #1 be the E clock
> line. Logic should be set so that teh address is decoded on the rising
> edge of the E clock. Make sure that the macrocell associated for A3 is
> also programmed for combinatorial mode and not registered mode.  

Well yes pin 1 is the clock, but I am using a decoded address to drive 
that pin after all I only want to latch D7 in at address ff40, this is 
however anded with E, and latched on rising edge.

Yep only on MC  as registered and that is the one connected to D7.
The odd thing is as I said in another post I get this weird behavior if 
A3 is meerly connected to a pin even if the internal logic does not use 
it which is most strange :)

> Word of caution on the MC6809E. The address bus output driver
> trtansistors are NMOS depletion load. That is the output transistor is
> a NMOS depletion transistor with another NMOS depletion transistor
> with the gate connected in diode fashion and this takes the place of
> the load resistor in the drain circuit. When driving a TTL compatible
> input to logic High, the 6809 can only source (current flowing out)
> about 400 microamps max. Driving the TTL input to a low the 6809 can
> sink (current flowing in) of 2 ma max. 

Well connected to there should be internal rom (the twom mask programmed 
ones have been replaced with an eprom). And the disk ROM in a cartrage, 
and of course the SAM, but that would be the same for the other address 
lines I am using too A0..A4.

> The problem is the Coco has so much already on the address buss
> internally that they had to add internal pullups to maintain the logic
> levels with the output high signals. By adding a pullup externally
> suggests that the PLD is requireing to much current when a login one
> is presented or the A3 line, the internal pullup resistor is not
> soldered properly or the A3 pin of the MPU is not to spec.
 >
> In the case of PLD requireing too much current for the MPU on logic
> high, you may have to add buffers to the address buss lines.

That I may have to do, though I do find itr odd that I see this 
behaviour on A3 on two machines well I have the CPLD version designed, 
just waiting for the chips to arrive now so hopefully with that I'll 
have less problems.

Phill.



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