[Coco] [Color Computer] USB project

[James Diffendaffer]

--- In ColorComputer at yahoogroups.com, "James Diffendaffer"
<jdiffendaffer at y...> wrote:
> --- In ColorComputer at yahoogroups.com, "James Diffendaffer"
> <jdiffendaffer at y...> wrote:
> > Given that fact, if I address it at FF70 the circuit looks like it can
> > be implemented with a 12 input NAND gate, a quad 2 input NAND gate, a
> > 3 to 8 decoder and a dual 4 input NOR gate.
> > I need to double check that though.  
> 
> Ok, the 3 to 8 decoder is only required to add additional hardware or
> switch the address above FF70-FF71 so I'm going to describe the
> circuit without it. 
> 
> Attach the R/W line from the CoCo to both inputs of one gate on the
> quad 2 input NAND.  This is an inverter and splits the R/W into
> separate R and W lines.  I think R is active low on the CoCo so you
> also connect the CoCo R/W line to /R on the Cypress chip and the
> output from the NAND to the /W line on the Cypress chip.  If the read
> is active high on the R/W line just reverse the connections on the
> Cypress /R and /W lines.


The CoCo write line is active low so it goes strait to the Cypress
write line and the read goes through the inverter.

The CoCo reset is active low and the Cypress chip's reset appears to
be active low as well so the CoCo reset is attached directly to the
Cypress reset.
 
The CoCo non maskable interrupt is active low and the Cypress
interrupt line appears to be active high on the diagram I'm looking at
(very small text).  So, the Cypress interrupt line goes to two unused
inputs on the quad 2 input NAND and the output goes to the CoCo NMI.

>From the timing diagrams it appears as if I should pass the CoCo E
Clock to the inputs of the last gate of the quad 2 input NAND and
attach the output to the /CS on the Cypress chip.

I would use a fast part for the quad 2 input NAND gate but I think the
speed of the other chips is less critical since the address lines are
valid before and after the E clock triggers I/O.  I'm not sure the
fast chip would be required but better safe than flaky hardware.

You will notice I attached multiple chip outputs to the /CS on the
Cypress Chip.  This creates an OR between those signals.  If any
signal is high then the Cypress chip is not active. 
If there is a problem with this when attaching a 3.3V part to TTL
logic please let me know.

The rest of the circuit is strait from the Cypress examples.  That
means the clock for the chip, it's outputs to the USB buss, etc.

Just add 3 capacitors for noise reduction and it should work.
Well... once the drivers are written anyway.





------------------------ Yahoo! Groups Sponsor --------------------~--> 
<font face=arial size=-1><a href="http://us.ard.yahoo.com/SIG=12hnepm1m/M=362329.6886308.7839368.1510227/D=groups/S=1705005378:TM/Y=YAHOO/EXP=1122767929/A=2894321/R=0/SIG=11dvsfulr/*http://youthnoise.com/page.php?page_id=1992
">Fair play? Video games influencing politics. Click and talk back!</a>.</font>
--------------------------------------------------------------------~-> 

Brought to you by the 6809, the 6803 and their cousins! 
Yahoo! Groups Links

<*> To visit your group on the web, go to:
    http://groups.yahoo.com/group/ColorComputer/

<*> To unsubscribe from this group, send an email to:
    ColorComputer-unsubscribe at yahoogroups.com

<*> Your use of Yahoo! Groups is subject to:
    http://docs.yahoo.com/info/terms/