[Coco] [Color Computer] USB project

[James Diffendaffer]

Ignore the latch comments.  The 'interfacing an external processor'
doc shows only one address input so I checked all the specs again. 
The part I'm using has the latch built in.  The doc file I was looking
at seemed to totally ignore that fact.  Not sure why.

Given that fact, if I address it at FF70 the circuit looks like it can
be implemented with a 12 input NAND gate, a quad 2 input NAND gate, a
3 to 8 decoder and a dual 4 input NOR gate.
I need to double check that though.  

--- In ColorComputer at yahoogroups.com, "James Diffendaffer"
<jdiffendaffer at y...> wrote:
> Well, it depends on the circuit I decide to implement.
> 
> The chip uses a full byte address range just for it's registers. 
> (example FF80-FF8F) That's a lot if I don't want it to interfere with
> anything else.
> 
> The alternative is to use a latch at one CoCo address to set the
> address on the chip and one CoCo address to access the registers/FIFO.  
> It only takes two CoCo addresses to implement that way but it's a more
> complex circuit than the other 8 bit computer implementations.  It
> also slows down access every time you need to switch registers and
> complicates interrupt handling unless the driver disables and enables
> interrupts a lot.
> 
> Either implementation is easy but board size is a concern.
> 
> At this point I need to sit down and read some sample code for the
> chip and see what the real impact the two byte interface will be.
> If it's too great it would only be usefull in a faster next gen coco
> design and a prototype would just let me work on drivers.  And that
> has to wait on several other things I want to do anyway.
> 
> There is some other hardware I want to implement in a CPLD but given
> my experience with VHDL/Verilog and the complexity of the circuit (at
> least 5 separate devices) that could take some time.
> I suppose I could implement it one piece at a time with the CPLD and I
> could implement both USB interfaces for testing.
> 
> <sigh> As soon as I get GCC working and these magazines scanned I'll
> do some estimates as to how big of a CPLD I'll need for everything.  
> I'll also send the circuit info to James and see what he thinks.  He'd
> probably have both on the CPLD in less than an hour... simple stuff.
> 
> --- In ColorComputer at yahoogroups.com, "John R. Hogerhuis"
> <jhoger at p...> wrote:
> > On Fri, 2005-07-29 at 22:48 +0100, Phill Harvey-Smith wrote:
> > > John R. Hogerhuis wrote:
> > 
> > > > If some kind of PLD, you could always defer this question and use
> > > > whatever mmio you need for now.
> > > 
> > > I believe when we discussed this a while back he said he wanted to
> use 
> > > standard LS type logic to make it easier for the home constuctor to 
> > > build as you don't need custom programmers etc.
> > > 
> > 
> > That's my recollection too (seems I remember ideas I disagree with
> > better than those where I agree). But I have half a memory of him
> > changing his mind, probably wrong, which is why I asked.
> > 
> > In any event, this kind of issue can be deferred when you do all logic
> > aside from power stuff in the CPLD or FPGA. We've been using CPLD
in our
> > hobbyist project at http://bitchin100.com/remem_project.htm . But we
> > have to since our board has to be crammed into a TRS-80 Model 100.
Also
> > we need several surface mount parts in any event.
> > 
> > -- John.




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